On 19-03-01 15:04:14, Peter Xu wrote:
[...]
> > @@ -3540,6 +3555,15 @@ static void vtd_init(IntelIOMMUState *s)
> > s->cap |= VTD_CAP_CM;
> > }
> >
> > +/* TODO: read cap/ecap from host to decide which cap to be exposed. */
> > +if (s->scalable_mode) {
> > +if
On 19-03-01 14:52:19, Peter Xu wrote:
> On Thu, Feb 28, 2019 at 09:47:55PM +0800, Yi Sun wrote:
> > From: "Liu, Yi L"
> >
> > Intel(R) VT-d 3.0 spec introduces scalable mode address translation to
> > replace extended context mode. This patch extends current emulator to
> > support Scalable Mode
On 19-03-01 14:59:00, Peter Xu wrote:
> On Thu, Feb 28, 2019 at 09:47:56PM +0800, Yi Sun wrote:
> > From: "Liu, Yi L"
> >
> > Per Intel(R) VT-d 3.0, the qi_desc is 256 bits in Scalable
> > Mode. This patch adds emulation of 256bits qi_desc.
> >
> > Signed-off-by: Liu, Yi L
> > [Yi Sun is
Here is the abstraction of current call flow of object_new_with_type()
object_initialize_with_type
type_initialize
object_initialize_with_type
type_initialize
This is not necessary to spread type_initialize in two places.
Signed-off-by: Wei Yang
---
Philippe Mathieu-Daudé writes:
> On 2/28/19 9:25 PM, Alex Bennée wrote:
>> From: Stefan Hajnoczi
>>
>> Test that 32-bit instructions declared UNDEFINED in the ARMv6-M
>> Reference Manual really do raise an exception. Also test that the 6
>> 32-bit instructions defined in the ARMv6-M
> From: Yi Sun [mailto:yi.y@linux.intel.com]
> Sent: Friday, March 1, 2019 3:13 PM
>
> On 19-03-01 15:07:34, Peter Xu wrote:
> > On Thu, Feb 28, 2019 at 09:47:54PM +0800, Yi Sun wrote:
> > > Intel vt-d rev3.0 [1] introduces a new translation mode called
> > > 'scalable mode', which enables
Max Filippov writes:
> Hi Alex,
>
> On Thu, Feb 28, 2019 at 12:25 PM Alex Bennée wrote:
>
> [...]
>
>> diff --git a/tests/tcg/xtensa/Makefile.softmmu-target
>> b/tests/tcg/xtensa/Makefile.softmmu-target
>> new file mode 100644
>> index 00..1a4014506f
>> --- /dev/null
>> +++
Marcel Apfelbaum writes:
> Hi Yuval,
>
> On 2/27/19 4:06 PM, Yuval Shaia wrote:
>> Allow interrogating device internals through HMP interface.
>> The exposed indicators can be used for troubleshooting by developers or
>> sysadmin.
>> There is no need to expose these attributes to a management
On 19-03-01 15:07:34, Peter Xu wrote:
> On Thu, Feb 28, 2019 at 09:47:54PM +0800, Yi Sun wrote:
> > Intel vt-d rev3.0 [1] introduces a new translation mode called
> > 'scalable mode', which enables PASID-granular translations for
> > first level, second level, nested and pass-through modes. The
>
On Thu, Feb 28, 2019 at 09:47:54PM +0800, Yi Sun wrote:
> Intel vt-d rev3.0 [1] introduces a new translation mode called
> 'scalable mode', which enables PASID-granular translations for
> first level, second level, nested and pass-through modes. The
> vt-d scalable mode is the key ingredient to
On Thu, Feb 28, 2019 at 09:47:57PM +0800, Yi Sun wrote:
> This patch adds an option to provide flexibility for user to expose
> Scalable Mode to guest. User could expose Scalable Mode to guest by
> the config as below:
>
> "-device intel-iommu,caching-mode=on,scalable-mode=on"
>
> The Linux
On Thu, Feb 28, 2019 at 09:47:56PM +0800, Yi Sun wrote:
> From: "Liu, Yi L"
>
> Per Intel(R) VT-d 3.0, the qi_desc is 256 bits in Scalable
> Mode. This patch adds emulation of 256bits qi_desc.
>
> Signed-off-by: Liu, Yi L
> [Yi Sun is co-developer to rebase and refine the patch.]
>
Patchew URL: https://patchew.org/QEMU/20190301064809.3074-1-llyzs@gmail.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190301064809.3074-1-llyzs@gmail.com
Subject: [Qemu-devel] [PATCH v2] slirp: check for ioctlsocket
On Thu, Feb 28, 2019 at 09:47:55PM +0800, Yi Sun wrote:
> From: "Liu, Yi L"
>
> Intel(R) VT-d 3.0 spec introduces scalable mode address translation to
> replace extended context mode. This patch extends current emulator to
> support Scalable Mode which includes root table, context table and new
Sometimes sorecvfrom() is called from slirp.c because revents == G_IO_IN,
but there is 0 bytes available and recvfrom could be blocking indefinitely.
This is likely due to 0-length udp payload. This also adds an error
checking for ioctlsocket.
Signed-off-by: Vic Lee
---
slirp/socket.c | 10
On 2/28/19 11:05 AM, David Hildenbrand wrote:
> So for writing from helpers, I can use probe_write(). What about testing
> write access from TCG code?
>
> I could do a load, followed by a store of the loaded value. This should
> work in most cases (but eventually could be observed by somebody
From: Michael Qiu
When using command -device virtio-vga,virgl=on
the default max_outputs is 0, this will lead coredump,
(con=0x0, hw_ops=0x564452e0 ,
opaque=0x5754ec60) at ui/console.c:1872
(vpci_dev=0x5754ec60, errp=0x7fffdbb8)
at
On Fri, Mar 01, 2019 at 12:13:08PM +0800, 08005...@163.com wrote:
> From: Michael Qiu
>
> When using command -device virtio-vga,virgl=on
> the default max_outputs is 0, this will lead coredump,
The default is 1.
> @@ -46,6 +46,11 @@ static void virtio_gpu_pci_realize(VirtIOPCIProxy
>
On Thu, Feb 28, 2019 at 11:53:43AM -0500, G 3 wrote:
> On Thu, Feb 28, 2019 at 12:01 AM Mark Cave-Ayland <
> mark.cave-ayl...@ilande.co.uk> wrote:
>
> > On 27/02/2019 05:27, Gerd Hoffmann wrote:
> >
> > > On Tue, Feb 26, 2019 at 04:11:06PM -0500, G 3 wrote:
> > >> When I use edid=on, I do see a
Hi,
> > Well, not really. EDID is about monitor capabilities. The monitor will
> > see 8 bit per color channel, no matter whenever your GPU composes that
> > signal using a 8bpp mode + color palette or 24bpp mode with direct
> > color.
>
> Hmmm okay. Perhaps it might still be worth hooking
Sometimes sorecvfrom() is called from slirp.c because revents == G_IO_IN,
but there is 0 bytes available and recvfrom could be blocking indefinitely.
This is likely due to 0-length udp payload. This also adds an error
checking for ioctlsocket.
Signed-off-by: Vic Lee
---
slirp/socket.c | 10
llyzs, le ven. 01 mars 2019 12:27:31 +0800, a ecrit:
> I believe this is because UDP packet can have 0 length payload.
Ah, right, that one makes sense indeed.
> I also found out that sometimes ioctlsocket() call can return error
> (probably caused by my unstable wifi linux driver), in which case
There are currently 3 mitigations the availability of which is controlled
by the spapr-caps mechanism, cap-cfpc, cap-sbbc, and cap-ibs. Enable these
mitigations by default for the pseries-4.0 machine type.
By now machine firmware should have been upgraded to allow these
settings.
Signed-off-by:
This series is based on the ppc-for-4.0 branch with my large-decrementer
and count-cache-flush series applied.
Suraj Jitindar Singh (2):
target/ppc/tcg: make spapr_caps apply cap-[cfpc/sbbc/ibs] non-fatal
for tcg
target/ppc/spapr: Enable mitigations by default for pseries-4.0
machine
The spapr_caps cap-cfpc, cap-sbbc and cap-ibs are used to control the
availability of certain mitigations to the guest. These haven't been
implemented under TCG, it is unlikely they ever will be, and it is unclear
as to whether they even need to be.
As such, make failure to apply these
Hi,
I believe this is because UDP packet can have 0 length payload. I
quote some resources here:
https://stackoverflow.com/questions/12505892/under-linux-can-recv-ever-return-0-on-udp
https://stackoverflow.com/questions/5307031/how-to-detect-receipt-of-a-0-length-udp-datagram
I also found out
On Fri, 2019-03-01 at 14:19 +1100, Suraj Jitindar Singh wrote:
> Introduce a new spapr_cap SPAPR_CAP_CCF_ASSIST to be used to indicate
> the requirement for a hw-assisted version of the count cache flush
> workaround.
>
> The count cache flush workaround is a software workaround which can
> be
>
> CC-ing John because of the keyword "incremental".
Ok
>
>On 14.02.19 07:43, mahaocong wrote:
>> From: mahaocong
>>
>> This patch adds possibility to start mirroring with user-created-bitmap.
>> On full mode, mirror create a non-named-bitmap by scanning whole block-
>> chain, and on top mode,
Currently we do device realization like below:
hotplug_handler_pre_plug()
dc->realize()
hotplug_handler_plug()
Before we do device realization and plug, we should allocate necessary
resources and check if memory-hotplug-support property is enabled.
At the piix4 and ich9, the
On Thu, Feb 28, 2019 at 12:28:22PM +, Dr. David Alan Gilbert wrote:
> * Daniel P. Berrangé (berra...@redhat.com) wrote:
> > On Thu, Feb 28, 2019 at 11:40:19AM +, Dr. David Alan Gilbert wrote:
> > > * Peter Xu (pet...@redhat.com) wrote:
> > > > On Wed, Feb 27, 2019 at 04:49:00PM +, Dr.
Introduce a new spapr_cap SPAPR_CAP_CCF_ASSIST to be used to indicate
the requirement for a hw-assisted version of the count cache flush
workaround.
The count cache flush workaround is a software workaround which can be
used to flush the count cache on context switch. Some revisions of
hardware
The spapr_cap SPAPR_CAP_IBS is used to indicate the level of capability
for mitigations for indirect branch speculation. Currently the available
values are broken (default), fixed-ibs (fixed by serialising indirect
branches) and fixed-ccd (fixed by diabling the count cache).
Introduce a new value
Patchew URL:
https://patchew.org/QEMU/20190301025140.4351-1-richardw.y...@linux.intel.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190301025140.4351-1-richardw.y...@linux.intel.com
Subject: [Qemu-devel] [PATCH v6] i386,
Currently we do device realization like below:
hotplug_handler_pre_plug()
dc->realize()
hotplug_handler_plug()
Before we do device realization and plug, we should allocate necessary
resources and check if memory-hotplug-support property is enabled.
At the piix4 and ich9, the
Implement support to allow KVM guests to take advantage of the large
decrementer introduced on POWER9 cpus.
To determine if the host can support the requested large decrementer
size, we check it matches that specified in the ibm,dec-bits device-tree
property. We also need to enable it in KVM by
Prior to POWER9 the decrementer was a 32-bit register which decremented
with each tick of the timebase. From POWER9 onwards the decrementer can
be set to operate in a mode called large decrementer where it acts as a
n-bit decrementing register which is visible as a 64-bit register, that
is the
Enable the large decrementer by default for the pseries-4.0 machine type.
It is disabled again by default_caps_with_cpu() for pre-POWER9 cpus
since they don't support the large decrementer.
Signed-off-by: Suraj Jitindar Singh
---
hw/ppc/spapr.c | 3 ++-
hw/ppc/spapr_caps.c | 5 +
2
Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the
availability of the large decrementer for a guest.
Signed-off-by: Suraj Jitindar Singh
---
hw/ppc/spapr.c | 2 ++
hw/ppc/spapr_caps.c| 17 +
include/hw/ppc/spapr.h | 5 -
3 files changed, 23
On Thu, Feb 28, 2019 at 03:12:21PM +0100, Igor Mammedov wrote:
>On Thu, 28 Feb 2019 09:13:25 +0800
>Wei Yang wrote:
>
>> On Wed, Feb 27, 2019 at 07:04:02PM +0100, Igor Mammedov wrote:
>> >On Mon, 25 Feb 2019 09:15:34 +0800
>> >Wei Yang wrote:
>> >
>> >> On Mon, Feb 25, 2019 at 09:07:08AM
After the introduction of generic PCIe root port and PCIe-PCI bridge,
we will also have SHPC controller on ARM, so just enalbe SHPC native
hot plug.
Cc: Shannon Zhao
Cc: Peter Maydell
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Signed-off-by: Heyi Guo
Signed-off-by: Heyi Guo
---
Hi Yongbok, Aleksandar.
(I believe this is the v6 of this patched, included in a v4 series).
On 2/26/19 1:55 PM, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> The optional Data Scratch Pad RAM (DSPRAM) block provides a general scratch
> pad RAM
> used for temporary storage of data. The
The first one is suggested by Igor Mammedov to provide rule for multiline
code.
The second is a trivial fix to make example code all indented with 4 spaces.
v5:
* mostly address function variants
v4:
* one exception case for function
v3:
* fix typo in both changelog and example
v2:
*
All the example code are indented with four spaces except this one.
Fix this by adding four spaces here.
Signed-off-by: Wei Yang
Reviewed-by: Eric Blake
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
---
CODING_STYLE | 8
1 file changed, 4 insertions(+), 4
We didn't specify the indent rule for multiline code here, which may
mislead users. And in current code, the code use various styles.
Add this rule in CODING_STYLE to make sure this is clear to every one.
Signed-off-by: Wei Yang
Suggested-by: Igor Mammedov
---
v5:
* different rules ->
On Thu, Feb 28, 2019 at 02:57:07PM +0100, Igor Mammedov wrote:
>On Thu, 28 Feb 2019 08:46:10 +0800
>Wei Yang wrote:
>
>> On Wed, Feb 27, 2019 at 06:27:49PM +0100, Igor Mammedov wrote:
>> >On Wed, 27 Feb 2019 13:59:20 +
>> >Wei Yang wrote:
>> >
>> >> On Wed, Feb 27, 2019 at 02:12:42PM
Quoting Thomas Huth (2019-02-28 12:40:52)
> On 26/02/2019 05.52, David Gibson wrote:
> > From: Michael Roth
> >
> > Extend the existing EPOW event format we use for PCI
> > devices to emit PHB plug/unplug events.
> >
> > Signed-off-by: Michael Roth
> > Reviewed-by: David Gibson
> >
On Thu, Feb 28, 2019 at 03:36:14PM +0100, Igor Mammedov wrote:
>On Mon, 25 Feb 2019 09:25:29 +0800
>Wei Yang wrote:
>
>> We didn't specify the indent rule for multiline code here, which may
>> mislead users. And in current code, the code use different rules.
>diffrent from what? I'd use "various
I got it. Many thanks.
Thanks,
Danmei
-Original Message-
From: Thomas Huth [mailto:th...@redhat.com]
Sent: Friday, March 1, 2019 12:42 AM
To: Wei, Danmei ; qemu-devel@nongnu.org
Cc: Hao, Xudong
Subject: Re: [Qemu-devel] Qemu build failure with uninitialized variables when
Hi Alex,
On Thu, Feb 28, 2019 at 12:25 PM Alex Bennée wrote:
[...]
> diff --git a/tests/tcg/xtensa/Makefile.softmmu-target
> b/tests/tcg/xtensa/Makefile.softmmu-target
> new file mode 100644
> index 00..1a4014506f
> --- /dev/null
> +++ b/tests/tcg/xtensa/Makefile.softmmu-target
> @@
On 3/1/19 12:24 AM, Max Filippov wrote:
> On Thu, Feb 28, 2019 at 2:54 PM Philippe Mathieu-Daudé
> wrote:
>
>> BTW is this simulator downloadable? I see the Zephyr project also uses
>> it, and I looked for it on https://ip.cadence.com/swdev but couldnt find
>> a (public) link.
>
> There's a
On Thu, Feb 28, 2019 at 2:54 PM Philippe Mathieu-Daudé
wrote:
> Max: I think it should be quite easy to port your simulator to Alex's
> new Makefile.
I agree.
> BTW is this simulator downloadable? I see the Zephyr project also uses
> it, and I looked for it on https://ip.cadence.com/swdev but
On 3/1/19 12:07 AM, Philippe Mathieu-Daudé wrote:
> Hi Alex,
>
> On 2/28/19 9:25 PM, Alex Bennée wrote:
>> Bare tests are standalone assembly tests that don't require linking to
>> any libc and hence can be built with kernel only compilers. The libc
>> tests need a compiler capable of building
Hi Alex,
On 2/28/19 9:25 PM, Alex Bennée wrote:
> Bare tests are standalone assembly tests that don't require linking to
> any libc and hence can be built with kernel only compilers. The libc
> tests need a compiler capable of building properly linked userspace
> binaries. As we don't have such a
The hardware singlestep mechanism in POWER works via a Trace Interrupt
(0xd00) that happens after any instruction executes, whenever MSR_SE =
1 (PowerISA Section 6.5.15 - Trace Interrupt).
However, with kvm_hv, the Trace Interrupt happens inside the guest and
KVM has no visibility of it.
For single stepping (via KVM) of a guest vcpu to work, KVM needs not
only to support the SET_GUEST_DEBUG ioctl but to also recognize the
KVM_GUESTDBG_SINGLESTEP bit in the control field of the
kvm_guest_debug struct.
This patch adds support for querying the single step capability so
that QEMU can
This is in preparation for a refactoring of the kvm_handle_debug
function in the next patch.
Signed-off-by: Fabiano Rosas
---
target/ppc/kvm.c | 47 ---
1 file changed, 28 insertions(+), 19 deletions(-)
diff --git a/target/ppc/kvm.c
Single stepping via GDB/gdbstub is currently not working with KVM
HV. When asking for a single step (stepi), KVM simply ignores the
request and execution continues.
This has the direct effect of breaking GDB's 'step', 'stepi', 'next',
'nexti' commands. The 'continue' command is also affected
Signed-off-by: Fabiano Rosas
Reviewed-by: Alexey Kardashevskiy
---
target/ppc/excp_helper.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 39bedbb11d..beafcf1ebd 100644
---
There are four scenarios being handled in this function:
- single stepping
- hardware breakpoints
- software breakpoints
- fallback (no debug supported)
A future patch will add code to handle specific single step and
software breakpoints cases so let's split each scenario into its own
function
On 2/28/19 9:25 PM, Alex Bennée wrote:
> From: Stefan Hajnoczi
>
> Test that 32-bit instructions declared UNDEFINED in the ARMv6-M
> Reference Manual really do raise an exception. Also test that the 6
> 32-bit instructions defined in the ARMv6-M Reference Manual do not raise
> an exception.
>
On 2/28/19 9:25 PM, Alex Bennée wrote:
> Signed-off-by: Alex Bennée
>
> ---
> v2
> - use cross CC for linker
> - fix up test selection to skip linker.ld.S
> ---
> tests/tcg/xtensa/Makefile| 93
> tests/tcg/xtensa/Makefile.softmmu-target | 40
On Mon, Feb 04, 2019 at 09:26:07PM +0100, Philippe Mathieu-Daudé wrote:
> Boston is built around a Xilinx FPGA, which includes a PCIe root port
> and an UART. An Intel EG20T PCH connects the I/O peripherals, but only
> the SATA bus is emulated.
>
> Signed-off-by: Philippe Mathieu-Daudé
Hi Alex,
On 2/28/19 9:25 PM, Alex Bennée wrote:
> The compilation flags for proper building are in the source tree. We
> also fix exit to 0 so the result is counted as a success.
>
> Signed-off-by: Alex Bennée
> ---
> tests/tcg/mips/Makefile.target | 11 ---
>
On Mon, Feb 25, 2019 at 5:24 AM Peter Maydell
wrote:
> The OSX Mojave release is more picky about enforcing the Cocoa API
> restriction that only the main thread may perform UI calls. To
> accommodate this we need to restructure the Cocoa code:
> * the special OSX main() creates a second thread
:18 +)
are available in the git repository at:
git://github.com/OSLL/qemu-xtensa.git tags/20190228-xtensa
for you to fetch changes up to de0cebd93089ff2ebf2ebf9d287381eb73cbb9aa:
tests/tcg/xtensa: add FPU2000 coprocessor tests (2019-02-28 04:43:24 -0
Opcodes in different slots may read and write same resources (registers,
states). In the absence of resource dependency loops it must be possible
to sort opcodes to avoid interference.
Record resources used by each opcode in the bundle. Build opcode
dependency graph and use topological sort to
Patchew URL: https://patchew.org/QEMU/20190228204638.4928-1-ekoh...@gmail.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190228204638.4928-1-ekoh...@gmail.com
Subject: [Qemu-devel] [PATCH] Use wide-character ncurses
Hi,
QEMU is unable to display all VGA characters to console output; for
instance, the smiley (VGA character 0x01) is printed just as
\001. However, QEMU links with the wide-character ncurses library,
which can output all VGA characters (since they have Unicode
equivalents). The attached patch
On Mon, Feb 25, 2019 at 5:24 AM Peter Maydell
wrote:
> The Cocoa UI should run on the main thread; this is enforced
> in OSX Mojave. In order to be able to run on the main thread,
> we need to make sure we hold the iothread lock whenever we
> call into various QEMU UI midlayer functions.
>
>
Hello,
llyzs, le jeu. 28 févr. 2019 19:59:12 +0800, a ecrit:
> Sometimes sorecvfrom() is called from slirp.c because revents == G_IO_IN,
> however inside sorecvfrom() function, ioctlsocket() returns 0 bytes available
> and recvfrom could be blocking indefinitely. This adds a non-blocking flag to
Patchew URL:
https://patchew.org/QEMU/20190228202537.4638-1-alex.ben...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190228202537.4638-1-alex.ben...@linaro.org
Subject: [Qemu-devel] [PATCH v2 00/16] Enabling
Hello,
Peter Maydell, le jeu. 28 févr. 2019 18:14:40 +, a ecrit:
> My guess is that this got a packed attribute mistakenly
> by analogy with the struct slirp_arphdr which is used in
> the ArpTable struct -- but that struct really is used to
> match on-the-wire data, and this one is not.
This
Signed-off-by: Alex Bennée
---
.travis.yml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index 71b3c4a7a3..90c5908ae1 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -255,6 +255,12 @@ matrix:
- ./configure ${CONFIG} --extra-cflags="-g3 -O0
This converts the existing Makefile into a Makefile.target and updates
it so it can be called by the tcg build system. The original Makefile
didn't set -cpu except for the v17 tests however that has broken (I
assume because linux-user is a "max" cpu) so here I force it to be
crisv17.
I've also
Bare tests are standalone assembly tests that don't require linking to
any libc and hence can be built with kernel only compilers. The libc
tests need a compiler capable of building properly linked userspace
binaries. As we don't have such a cross compiler at the moment we
won't be building those
Evidently upstream gcc doesn't like this opcode.
Signed-off-by: Alex Bennée
---
tests/tcg/cris/bare/check_btst.s | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/tests/tcg/cris/bare/check_btst.s b/tests/tcg/cris/bare/check_btst.s
index e39fc8f4d6..485deb2006
While used by TCG it is not explicitly part of TCG and the tests can
be run standalone in a minimal build.
Signed-off-by: Alex Bennée
---
.travis.yml| 6 ++
tests/Makefile.include | 2 +-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/.travis.yml b/.travis.yml
From: Stefan Hajnoczi
Test that 32-bit instructions declared UNDEFINED in the ARMv6-M
Reference Manual really do raise an exception. Also test that the 6
32-bit instructions defined in the ARMv6-M Reference Manual do not raise
an exception.
Based-on:
This is a mini library which provides helper functions to the tests
which are all currently written in assembly. A bunch of minor changes:
- removed libc related headers (fedora-cris-cross is a system compiler)
- re-organised the functions to avoid forward declarations
- cleaned
With this you can launch a test in gdb with:
cd $(BUILD)/tests
make -f $(SRC)/tests/tcg/Makefile gdb-$(TEST_NAME)
Signed-off-by: Alex Bennée
---
tests/tcg/Makefile | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/tcg/Makefile b/tests/tcg/Makefile
index 097e6374ea..47f4298e68
To avoid:
Error: dangerous MULS/MULU location; give it higher alignment
Signed-off-by: Alex Bennée
---
tests/tcg/cris/bare/check_mulx.s | 11 +++
1 file changed, 11 insertions(+)
diff --git a/tests/tcg/cris/bare/check_mulx.s b/tests/tcg/cris/bare/check_mulx.s
index
The compilation flags for proper building are in the source tree. We
also fix exit to 0 so the result is counted as a success.
Signed-off-by: Alex Bennée
---
tests/tcg/mips/Makefile.target | 11 ---
tests/tcg/mips/hello-mips.c| 2 +-
2 files changed, 5 insertions(+), 8 deletions(-)
Signed-off-by: Alex Bennée
---
v2
- use cross CC for linker
- fix up test selection to skip linker.ld.S
---
tests/tcg/xtensa/Makefile| 93
tests/tcg/xtensa/Makefile.softmmu-target | 40 ++
2 files changed, 40 insertions(+), 93 deletions(-)
From: Philippe Mathieu-Daudé
Xtensa cpu supported:
- dc232b
- dc233c
- csp
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
---
v2
- the compiler only works for system tests (no libc)
---
.../dockerfiles/debian-xtensa-cross.docker| 31 +++
This will allow tests to modify the QEMU invocation with for example
different -cpu stazas without having to define a whole new set of
runner types.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
v2
- default QEMU_OPTS to --monitor none for system emulation
---
Signed-off-by: Alex Bennée
---
tests/docker/dockerfiles/fedora-cris-cross.docker | 8
1 file changed, 8 insertions(+)
create mode 100644 tests/docker/dockerfiles/fedora-cris-cross.docker
diff --git a/tests/docker/dockerfiles/fedora-cris-cross.docker
Hi,
This is the second version of my system tests for TCG. We actually
only enable system tests for ARM and Xtensa but the framework is all
there for adding the others. I thought I'd get this out for comment
before starting on some softmmu tests for my demacro series. Also in
this set:
- add
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
tests/tcg/Makefile | 17 -
tests/tcg/Makefile.include | 2 +-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/tests/tcg/Makefile b/tests/tcg/Makefile
index bf06415390..55feab0f67 100644
---
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
Makefile.target| 2 --
tests/Makefile.include | 7 +++
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/Makefile.target b/Makefile.target
index 3b79e7074c..61b8be31a2 100644
--- a/Makefile.target
+++
This adds a handler for ibm,get-vpd RTAS calls, allowing pseries guest
to collect host information. It is disabled by default to avoid unwanted
information leakage. To enable it, use:
‘-M pseries,host-serial={passthrough|string},host-model={passthrough|string}’
Only the SE and TM keywords are
On 28.02.19 19:22, Richard Henderson wrote:
> On 2/28/19 2:54 AM, David Hildenbrand wrote:
>> Hmm, as v2 and v3 are handled concatenated it is not that easy. I am not
>> sure if we can handle this without a temporary vector.
>>
>> I thought about packing them first interleaved
>>
>> v2 = [v2e0,
On 28.02.19 18:15, Richard Henderson wrote:
> On 2/28/19 12:36 AM, David Hildenbrand wrote:
>> On 27.02.19 17:02, Richard Henderson wrote:
>>> On 2/26/19 3:38 AM, David Hildenbrand wrote:
Also fairly easy to implement. One issue we have is that exceptions will
result in some vectors
in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20190228-1
>
> for you to fetch changes up to 1c9af3a9e05c1607a36df4943f8f5393d7621a91:
>
> linux-user: Enable HWCAP_ASIMDF
On 26/02/2019 05.52, David Gibson wrote:
> From: Michael Roth
>
> Extend the existing EPOW event format we use for PCI
> devices to emit PHB plug/unplug events.
>
> Signed-off-by: Michael Roth
> Reviewed-by: David Gibson
> Signed-off-by: Greg Kurz
> Message-Id:
>
On Thu, Feb 28, 2019 at 06:22:02PM +0100, Kevin Wolf wrote:
> Am 28.02.2019 um 18:04 hat Sergio Lopez geschrieben:
> > On Thu, Feb 28, 2019 at 04:50:53PM +0100, Kevin Wolf wrote:
> > > Am 28.02.2019 um 16:01 hat Sergio Lopez geschrieben:
> > > > On Wed, Feb 27, 2019 at 06:37:14PM +0100, Kevin Wolf
On 2/27/19 10:20 AM, Daniel P. Berrangé wrote:
> This series provides the NBD parts of the authorization control series
> previously posted as:
>
> v1: https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg04482.html
> v2: https://lists.gnu.org/archive/html/qemu-devel/2018-06/msg05727.html
On Thu, 28 Feb 2019 at 17:57, Greg Kurz wrote:
>
> Build fails with gcc 9:
>
> CC hw/usb/dev-mtp.o
> hw/usb/dev-mtp.c: In function ‘usb_mtp_write_metadata’:
> hw/usb/dev-mtp.c:1754:36: error: taking address of packed member of ‘struct
> ’ may result in an unaligned pointer value
>
On 2/28/19 12:18 PM, Daniel P. Berrangé wrote:
>> It doesn't hold up this patch, but I note that with the qemu QMP command
>> changes you make in 2/3, you document that the object can be
>> created/removed on the fly, and the server will adjust which clients can
>> then subsequently connect. Is
On 2/28/19 2:54 AM, David Hildenbrand wrote:
> Hmm, as v2 and v3 are handled concatenated it is not that easy. I am not
> sure if we can handle this without a temporary vector.
>
> I thought about packing them first interleaved
>
> v2 = [v2e0, v2e1]
> v3 = [v3e0, ve31]
> v1 = [v2e0_packed,
On 2/27/19 10:43 AM, Eric Blake wrote:
>> @example
>> qemu-nbd \
>>--object tls-creds-x509,id=tls0,endpoint=server,dir=/path/to/qemutls \
>> - --tls-creds tls0 -t -x subset -p 10810 \
>> + --object 'authz-simple,id=auth0,identity=CN=laptop.example.com,,\
>> +O=Example
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