Hello Harsh,
On 10/1/24 11:28, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing the arch specific code for the now deprecated machine types.
v2: Addressed review comments from Cedric
v1: <2
On Wed, 2024-08-07 at 14:43 +0200, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> linux-user/strace.c | 19 +++
> linux-user/strace.list | 2 +-
> 2 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/linux-user/strace.c b/linux-user
On 10/1/24 11:29, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.11 specific code with this patch.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
Reviewed-
On 10/1/24 11:29, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.10 specific code with this patch for now.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
R
On 10/1/24 11:29, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.9 specific code with this patch for now.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
Re
On 10/1/24 11:29, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.8 specific code with this patch for now.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
Re
On 10/1/24 11:29, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.7 specific code with this patch for now.
While at it, also remove pre-2.8-migration hacks introduced for backward
On 10/1/24 11:29, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.6 specific code with this patch for now.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
Re
On 10/1/24 11:29, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.5 specific code with this patch for now.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
---
On 10/1/24 11:29, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.4 specific code with this patch for now.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
---
On 10/1/24 11:29, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.3 specific code with this patch for now.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
---
On 10/1/24 11:29, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.2 specific code with this patch for now.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
Re
On 10/1/24 11:29, Harsh Prateek Bora wrote:
Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.1 specific code with this patch for now.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
Re
marcandre.lur...@redhat.com writes:
> From: Marc-André Lureau
>
> object_resolve_path_type() didn't always set *ambiguousp.
>
> Signed-off-by: Marc-André Lureau
Fixes: 81c48dd79655 (hw/i386/acpi: Add object_resolve_type_unambiguous to
improve modularity)
> ---
> qom/object.c | 5 -
> 1 f
On Sep 26 15:45, Changqi Lu wrote:
> Add reservation acquire, reservation register,
> reservation release and reservation report commands
> in the nvme device layer.
>
> By introducing these commands, this enables the nvme
> device to perform reservation-related tasks, including
> querying keys, q
Peter Xu writes:
> On Tue, Oct 01, 2024 at 03:25:14PM +0100, Daniel P. Berrangé wrote:
>> On Tue, Oct 01, 2024 at 07:46:09AM +0200, Markus Armbruster wrote:
>> > Command query-migrationthreads went in without a QAPI ACK. Issues
>> > review should have caught:
>> >
>> > * Flawed documentation.
From: Mark Corbin
Included the prototype for the 'target_cpu_set_tls' function in the
'target_arch.h' header file. This function is responsible for setting
the Thread Local Storage (TLS) register for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richar
From: Mark Corbin
Implemented the 'setup_sigtramp' function for setting up the signal
trampoline code in the RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
Message-ID: <20240916155119.14610-8-itac...@freebsd.org>
Signed-off-by: Alista
From: Mark Corbin
Added the 'get_mcontext' function to extract and populate
the RISC-V machine context from the CPU state.
This function is used to gather the current state of the
general-purpose registers and store it in a 'target_mcontext_'
structure.
Signed-off-by: Mark Corbin
Signed-off-by:
From: Milan P. Stanić
build fails on musl libc (alpine linux) with this error:
../util/cpuinfo-riscv.c: In function 'cpuinfo_init':
../util/cpuinfo-riscv.c:63:21: error: '__NR_riscv_hwprobe' undeclared (first
use in this function); did you mean 'riscv_hwprobe'?
63 | if (syscall(__NR_
From: Mark Corbin
Implemented the RISC-V CPU execution loop, including handling various
exceptions and system calls. The loop continuously executes CPU
instructions,processes exceptions, and handles system calls by invoking
FreeBSD syscall handlers.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
From: Andrew Jones
Just as the hart bit setting of the AIA should be calculated as
ceil(log2(max_hart_id + 1)) the group bit setting should be
calculated as ceil(log2(max_group_id + 1)). The hart bits are
implemented by passing max_hart_id to find_last_bit() and adding
one to the result. Do the s
From: Mark Corbin
Added functions for setting up the RISC-V signal trampoline and signal
frame:
'set_sigtramp_args()': Configures the RISC-V CPU state with arguments
for the signal handler. It sets up the registers with the signal
number,pointers to the signal info and user context, the signal h
From: Thomas Huth
If QEMU has been configured with "--without-default-devices", the build
is currently failing with:
/usr/bin/ld: libqemu-riscv32-softmmu.a.p/target_riscv_cpu_helper.c.o:
in function `riscv_cpu_do_interrupt':
.../qemu/target/riscv/cpu_helper.c:1678:(.text+0x2214): undefined
From: Warner Losh
Added configuration for RISC-V 64-bit target to the build system.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
Message-ID: <20240916155119.14610-18-itac...@freebsd.org>
Signed-off-by: Alistair Francis
---
configs/targets/riscv64-bsd-
From: Mark Corbin
Introduced RISC-V specific ELF definitions and hardware capability
detection.
Additionally, a function to retrieve hardware capabilities
('get_elf_hwcap') is implemented, which returns the common bits set in
each CPU's ISA strings.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
From: Andrew Jones
C doesn't extend the sign bit for unsigned types since there isn't a
sign bit to extend. This means a promotion of a u32 to a u64 results
in the upper 32 bits of the u64 being zero. If that result is then
used as a mask on another u64 the upper 32 bits will be cleared. rv32
phy
From: Mark Corbin
Added definitions for RISC-V register structures, including
general-purpose registers and floating-point registers, in
'target_arch_reg.h'. Implemented the 'target_copy_regs' function to
copy register values from the CPU state to the target register
structure, ensuring proper en
The following changes since commit 718780d20470c66a3a36d036b29148d5809dc855:
Merge tag 'pull-nvme-20241001' of https://gitlab.com/birkelund/qemu into
staging (2024-10-01 11:34:07 +0100)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-risc
From: Alistair Francis
The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc
and Zbs bit-manipulation sub-extensions ratified in
v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable
them in QEMU as well.
1: https://github.com/lowRISC/opentitan/pull/9748
Signed-off-by: Alis
From: Mark Corbin
Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn'
functions for RISC-V architecture,
Both functions ensure that the CPU state and user context are properly
managed.
Signed-off-by: Mark Corbin
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Co-author
From: Mark Corbin
Implemented functions for setting up and initializing threads in the
RISC-V architecture.
The 'target_thread_set_upcall' function sets up the stack pointer,
program counter, and function argument for new threads.
The 'target_thread_init' function initializes thread registers bas
From: Mark Corbin
Introduced definitions for the RISC-V system call interface, including
the 'target_pt_regs' structure that outlines the register storage
layout during a system call.
Added constants for hardware machine identifiers.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-aut
From: Mark Corbin
Added definitions for RISC-V signal handling, including structures
and constants for managing signal frames and context
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by: Warner Losh
Reviewed-by: Richard Henderson
Message-ID: <20240916155119.14610-14-itac
From: Mark Corbin
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
Message-ID: <20240916155119.14610-4-itac...@freebsd.org>
Signed-off-by: Alistair Francis
---
From: Haibo Xu
As per the step 5 in the process documented in bios-tables-test.c,
generate the expected ACPI SRAT AML data file for RISC-V using the
rebuild-expected-aml.sh script and update the
bios-tables-test-allowed-diff.h.
This is a new file being added for the first time. Hence, iASL diff
From: Mark Corbin
Added definitions for RISC-V VM parameters, including maximum and
default sizes for text, data, and stack, as well as address space
limits.
Implemented helper functions for retrieving and setting specific
values in the CPU state, such as stack pointer and return values.
Signed-
From: Tomasz Jeznach
The IMSIC state variable eistate[] is modified by CSR instructions
within a range dedicated to the local CPU and by MMIO writes from any CPU.
Access to eistate from MMIO accessors is protected by the BQL, but
read-modify-write (RMW) sequences from CSRRW do not acquire the BQL
From: Warner Losh
Added a generic definition for RISC-V64 target-specific details.
Implemented the 'regpairs_aligned' function,which returns 'false'
to indicate that register pairs are not aligned in the RISC-V64 ABI.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard H
From: Alvin Chang
According to RISC-V Debug specification, the optional textra32 and
textra64 trigger CSRs can be used to configure additional matching
conditions for the triggers. For example, if the textra.MHSELECT field
is set to 4 (mcontext), this trigger will only match or fire if the low
bi
From: Mark Corbin
Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch'
system call for the RISC-V architecture.
Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that
the operation is not supported.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed
From: Mark Corbin
Added the initial implementation for RISC-V CPU initialization and main
loop. This includes setting up the general-purpose registers and
program counter based on the provided target architecture definitions.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by
From: Alexandre Ghiti
The Svvptc extension describes a uarch that does not cache invalid TLB
entries: that's the case for qemu so there is nothing particular to
implement other than the introduction of this extension.
Since qemu already exposes Svvptc behaviour, let's enable it by default
since
From: Samuel Holland
When riscv_load_firmware() loads an ELF, the ELF segment addresses are
used, not the passed-in firmware_load_addr. The machine models assume
the firmware entry point is what they provided for firmware_load_addr,
and use that address to generate the boot ROM, so if the ELF is
From: Andrew Jones
While the spec doesn't state it, setting timecmp to UINT64_MAX is
another way to stop a timer, as it's considered setting the next
timer event to occur at infinity. And, even if the time CSR does
eventually reach UINT64_MAX, the very next tick will bring it back to
zero, once a
From: Jason Chien
RVV spec allows implementations to set vl with values within
[ceil(AVL/2),VLMAX] when VLMAX < AVL < 2*VLMAX. This commit adds a
property "rvv_vl_half_avl" to enable setting vl = ceil(AVL/2). This
behavior helps identify compiler issues and bugs.
Signed-off-by: Jason Chien
Revi
From: Daniel Henrique Barboza
Gitlab issue [1] reports a misleading error when trying to run a 'rv64'
cpu with 'zfinx' and without 'f':
$ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false
qemu-system-riscv64: Zfinx cannot be supported together with F extension
The user
From: Haibo Xu
As per process documented (steps 1-3) in bios-tables-test.c, add
empty AML data file for RISC-V ACPI SRAT table and add the entry
in bios-tables-test-allowed-diff.h.
Signed-off-by: Haibo Xu
Reviewed-by: Sunil V L
Acked-by: Alistair Francis
Message-ID:
<0e30216273f2f59916bc6513
From: Alvin Chang
This commit allows program to write textra trigger CSR for type 2, 3, 6
triggers. In this preliminary patch, the textra.MHVALUE and the
textra.MHSELECT fields are allowed to be configured. Other fields, such
as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired t
From: Haibo Xu
Add ACPI SRAT table test case for RISC-V when NUMA was enabled.
Signed-off-by: Haibo Xu
Reviewed-by: Sunil V L
Acked-by: Alistair Francis
Message-ID:
Signed-off-by: Alistair Francis
---
tests/qtest/bios-tables-test.c | 28
1 file changed, 28 ins
When the emulated CPU reads or writes to a memory location
a) for which no read/write permissions exists, *and*
b) the access happens unaligned (non-natural alignment),
then the CPU should either
- trigger a permission fault, or
- trigger an unalign access fault.
In the current code the alignment
Add an additional test to further exercise the IOMMU where we attempt to
initialize the command, fault and page-request queues.
These steps are taken from chapter 6.2 of the RISC-V IOMMU spec,
"Guidelines for initialization". It emulates what we expect from the
software/OS when initializing the IO
Add a simple guideline to use the existing RISC-V IOMMU support we just
added.
This doc will be updated once we add the riscv-iommu-sys device.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
docs/specs/index.rst | 1 +
docs/specs/riscv-iommu.rst | 90 ++
From: Tomasz Jeznach
The RISC-V IOMMU can be modelled as a PCIe device following the
guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU
as a PCIe device".
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair F
Hi,
We had problems right at the finish line of the pull request due to endianness
problems reported in the Gitlab CI [1]. This triggered discussions in the
middle of the pull request patches [2] that resulted in this new version.
We dealt with the endianness problem that was hitting the Gitlab C
From: Tomasz Jeznach
DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
tr_response.
The DBG cap is always enabled. No on/off toggle is provided for it.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair F
From: Tomasz Jeznach
Extend memory transaction attributes with process identifier to allow
per-request address translation logic to use requester_id / process_id
to identify memory mapping (e.g. enabling IOMMU w/ PASID translations).
Signed-off-by: Tomasz Jeznach
Reviewed-by: Frank Chang
Revie
From: Tomasz Jeznach
Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
This will add support for ATS translation requests in Fault/Event
queues, Page-request queue and IOATC invalidations.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Fr
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
Add the foundation of the device emulation for RISC-V
From: Tomasz Jeznach
This header will be used by the RISC-V IOMMU emulation to be added
in the next patch. Due to its size it's being sent in separate for
an easier review.
One thing to notice is that this header can be replaced by the future
Linux RISC-V IOMMU driver header, which would become
From: Tomasz Jeznach
The RISC-V IOMMU spec predicts that the IOMMU can use translation caches
to hold entries from the DDT. This includes implementation for all cache
commands that are marked as 'not implemented'.
There are some artifacts included in the cache that predicts s-stage and
g-stage e
To test the RISC-V IOMMU emulation we'll use its PCI representation.
Create a new 'riscv-iommu-pci' libqos device that will be present with
CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this
device will only be consumed by the RISC-V libqos machine.
Start with basic tests: a PC
From: Tomasz Jeznach
Generate device tree entry for riscv-iommu PCI device, along with
mapping all PCI device identifiers to the single IOMMU device instance.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
---
hw/r
The RISC-V IOMMU PCI device we're going to add next is a reference
implementation of the riscv-iommu spec [1], which predicts that the
IOMMU can be implemented as a PCIe device.
However, RISC-V International (RVI), the entity that ratified the
riscv-iommu spec, didn't bother assigning a PCI ID for
On 10/1/24 8:28 PM, Tomasz Jeznach wrote:
On Tue, Sep 3, 2024 at 4:46 AM Daniel Henrique Barboza
wrote:
On 8/26/24 11:18 PM, Tomasz Jeznach wrote:
On Fri, Aug 23, 2024 at 5:42 AM Daniel Henrique Barboza
wrote:
On 8/20/24 12:16 PM, Jason Chien wrote:
Hi Daniel,
(...)
On Tue, Sep 3, 2024 at 4:46 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 8/26/24 11:18 PM, Tomasz Jeznach wrote:
> > On Fri, Aug 23, 2024 at 5:42 AM Daniel Henrique Barboza
> > wrote:
> >>
> >>
> >>
> >> On 8/20/24 12:16 PM, Jason Chien wrote:
> >>> Hi Daniel,
> >>>
> >>> On 2024/8/1 下午 11:43, Da
On 10/1/24 7:24 PM, Tomasz Jeznach wrote:
On Tue, Sep 24, 2024 at 3:18 PM Alistair Francis wrote:
+
+/* IOMMU index for transactions without process_id specified. */
+#define RISCV_IOMMU_NOPROCID 0
+
+static uint8_t riscv_iommu_get_icvec_vector(uint32_t icvec, uint32_t vec_type)
+{
+swi
On Tue, 1 Oct 2024, Bernhard Beschow wrote:
Am 15. August 2024 19:01:47 UTC schrieb Bernhard Beschow :
Am 16. Juli 2024 12:07:57 UTC schrieb BALATON Zoltan :
Add booke206_set_tlb() utility function and use it to replace very
similar create_initial_mapping functions in e500 machines.
Signed-off
On Tue, Oct 1, 2024 at 4:00 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 10/1/24 7:14 PM, Tomasz Jeznach wrote:
> > On Sun, Sep 29, 2024 at 8:46 AM Peter Maydell
> > wrote:
> >>
> >> On Sat, 28 Sept 2024 at 22:01, Daniel Henrique Barboza
> >> wrote:
> >>>
> >>>
> >>>
> >>> On 9/28/24 5:22 PM, P
Le 01/10/2024 à 17:14, Michael Vogt a écrit :
This commit adds support for the `openat2()` to `QEMU_STRACE`. It
will use the `openat2.h` header if available to create user
readable flags for the `resolve` argument but does not require
the header otherwise.
It also makes `copy_struct_from_user()`
On 10/1/24 7:14 PM, Tomasz Jeznach wrote:
On Sun, Sep 29, 2024 at 8:46 AM Peter Maydell wrote:
On Sat, 28 Sept 2024 at 22:01, Daniel Henrique Barboza
wrote:
On 9/28/24 5:22 PM, Peter Maydell wrote:
On Tue, 24 Sept 2024 at 23:19, Alistair Francis wrote:
+/* Register helper function
On Tue, Sep 24, 2024 at 3:18 PM Alistair Francis wrote:
> +
> +/* IOMMU index for transactions without process_id specified. */
> +#define RISCV_IOMMU_NOPROCID 0
> +
> +static uint8_t riscv_iommu_get_icvec_vector(uint32_t icvec, uint32_t
> vec_type)
> +{
> +switch (vec_type) {
> +case RI
This patch implements Allwinner A10 SPI controller emulation.
Only master-mode functionality is implemented.
Since U-Boot and Linux SPI drivers for Allwinner A10 perform only
byte-wide CPU access (no DMA) to the transmit and receive registers of
the peripheral, the emulated controller does not imp
The Allwinner A10 SPI controller is added to the Allwinner A10
description, so it is available when Cubieboard is emulated.
Update the documentation for Cubieboard to indicate SPI availability.
Signed-off-by: Strahinja Jankovic
---
docs/system/arm/cubieboard.rst | 1 +
hw/arm/Kconfig
On Sun, Sep 29, 2024 at 8:46 AM Peter Maydell wrote:
>
> On Sat, 28 Sept 2024 at 22:01, Daniel Henrique Barboza
> wrote:
> >
> >
> >
> > On 9/28/24 5:22 PM, Peter Maydell wrote:
> > > On Tue, 24 Sept 2024 at 23:19, Alistair Francis
> > > wrote:
>
> > >> +/* Register helper functions */
> > >> +
This patch set introduces the SPI controller emulation for Allwinner A10
SoC and Cubieboard.
Only master-mode functionality of the SPI controller is implemented.
Since U-Boot and Linux SPI drivers for Allwinner A10 perform only
byte-wide CPU access to the transmit and receive registers of the
con
On Tue, Oct 01, 2024 at 10:41:14PM +0200, Maciej S. Szmigiero wrote:
> On 30.09.2024 23:57, Peter Xu wrote:
> > On Mon, Sep 30, 2024 at 09:25:54PM +0200, Maciej S. Szmigiero wrote:
> > > On 27.09.2024 02:53, Peter Xu wrote:
> > > > On Fri, Sep 27, 2024 at 12:34:31AM +0200, Maciej S. Szmigiero wrote
On 30.09.2024 23:57, Peter Xu wrote:
On Mon, Sep 30, 2024 at 09:25:54PM +0200, Maciej S. Szmigiero wrote:
On 27.09.2024 02:53, Peter Xu wrote:
On Fri, Sep 27, 2024 at 12:34:31AM +0200, Maciej S. Szmigiero wrote:
On 20.09.2024 18:45, Peter Xu wrote:
On Fri, Sep 20, 2024 at 05:23:08PM +0200, Ma
On Tue, Oct 1, 2024 at 11:24 AM Peter Maydell
wrote:
> On Mon, 30 Sept 2024 at 22:28, Strahinja Jankovic
> wrote:
> >
> > Hi Peter,
> >
> > Thank you very much for the review and detailed comments.
> >
> > I will try to address all comments in the v2 of the patches, but I have
> some questions I
FWIW, I left a comment on the bug report asking for guidance, because it
seems to me that just reverting the commit mentioned above isn't the
right solution (as we'd be reintroducing the bug fixed by the commit).
--
You received this bug notification because you are a member of qemu-
devel-ml, wh
Am 15. August 2024 19:01:47 UTC schrieb Bernhard Beschow :
>
>
>Am 16. Juli 2024 12:07:57 UTC schrieb BALATON Zoltan :
>>Add booke206_set_tlb() utility function and use it to replace very
>>similar create_initial_mapping functions in e500 machines.
>>
>>Signed-off-by: BALATON Zoltan
>>---
>> hw
Borrow the code for formatting the most frequent WIFEXITED() and
WIFSIGNALED() special cases from from the strace's printstatus().
Output examples:
474729 wait4(-1,0x7f00767ff0a0,0,(nil)) = 474733 (wstatus={WIFEXITED(s) &&
WEXITSTATUS(s) == 1})
475833 wait4(-1,0x7f7de61ff0a0,0,(nil)) = 4
Am 24. September 2024 20:02:31 UTC schrieb Bernhard Beschow :
>
>
>Am 23. September 2024 10:38:46 UTC schrieb BALATON Zoltan :
>>On Mon, 23 Sep 2024, Bernhard Beschow wrote:
>>> The device model already has a header file. Also extract its implementation
>>> into
>>> an accompanying source file
On Tue, Jul 23, 2024 at 12:50 PM Akihiko Odaki
wrote:
> Commit 2523baf7fb4d ("qemu-keymap: Make references to allocations
> static") made references to allocations static to ensure LeakSanitizer
> can track them. This trick unfortunately did not work with gcc version
> 14.0.1; that compiler is cl
Le 01/10/2024 à 17:14, Michael Vogt a écrit :
This commit adds support for the `openat2()` syscall in the
`linux-user` userspace emulator.
It is implemented by extracting a new helper `maybe_do_fake_open()`
out of the exiting `do_guest_openat()` and share that with the
new `do_guest_openat2()`.
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Refactor to use the recently introduced ld/st_endian_pci_dma()
API. No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/tulip.c | 32 ++--
1 file changed, 10 insertions(+), 22 deletions(-)
d
On Tue, Oct 01, 2024 at 03:09:29PM +0300, Manos Pitsidianakis wrote:
> On Tue, Oct 1, 2024, 12:14 PM Thomas Huth wrote:
>
> > On 01/10/2024 10.50, Manos Pitsidianakis wrote:
> > > Hello Thomas,
> > >
> > > On Mon, 30 Sep 2024 20:18, Thomas Huth wrote:
> > >> Shortly after we switched to the orig
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Introduce the ld/st_endian_pci_dma() API, which takes an extra
boolean argument to dispatch to ld/st_{be,le}_pci_dma() methods.
Signed-off-by: Philippe Mathieu-Daudé
---
TODO: Update docstring regexp
---
include/hw/pci/pci_device.h | 24
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Define both endianness variants with a single macro.
Useful to add yet other endian specific definitions
in the next commit.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/pci/pci_device.h | 13 +++--
1 file changed, 7 insertion
The 'mainstone' machine has been deprecated since 9.0, and
so we can remove it for the 9.2 release.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240903160751.4100218-11-peter.mayd...@linaro.org
---
MAINTAINERS | 2 -
docs/system/ar
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Introduce the ld/st_endian_phys() API, which takes an extra
boolean argument to dispatch to ld/st_{be,le}_phys() methods.
Signed-off-by: Philippe Mathieu-Daudé
---
TODO: Update docstring regexp
---
include/exec/memory_ldst_phys.h.inc | 66 ++
Remove the pxa2xx-specific GPIO device.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240903160751.4100218-22-peter.mayd...@linaro.org
---
include/hw/arm/pxa.h | 5 -
hw/arm/pxa2xx_gpio.c | 365 ---
hw/arm/meson.build
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Refactor to use the recently introduced ld/st_endian_phys() API.
No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/virtio/virtio-access.h | 27 +--
1 file changed, 5 insertions(+), 22 delet
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Refactor to use the recently introduced ld/st_endian_p() API
No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/tcg/plugins/mem.c | 24 ++--
1 file changed, 6 insertions(+), 18 deletions(-)
diff --g
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Add the BlCpuCfg::cpu_is_bigendian field, initialize it in
machine code. Bootloader API use the ld/st_endian_p() to
dispatch to target endianness.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 1 +
hw/mips/bootloader
The MAINSTONE_FPGA device was used only by the 'mainstone' machine
type, so we can remove it now.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20240903160751.4100218-12-peter.mayd...@linaro.org
---
MAINTAINERS | 1 -
hw/misc/mst_fpga.c | 269 --
The omap_dma4 device was only used in the OMAP2 SoC, which has
been removed.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-id: 20240903160751.4100218-53-peter.mayd...@linaro.org
---
include/hw/arm/omap.h | 1 -
hw/dma/omap_dma.c
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Move code evaluation from preprocessor to compiler so
both if() ladders are processed. Mostly style change.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/xtensa/xtfpga.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --
The pxa27x-timer can be removed now we have removed the PXA2xx
SoC models. The pxa25x-timer device must remain as it is still
used by strongarm.
Signed-off-by: Peter Maydell
Message-id: 20240903160751.4100218-24-peter.mayd...@linaro.org
---
hw/timer/pxa2xx_timer.c | 24
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Introduce the ld/st_endian_p() API, which takes an extra
boolean argument to dispatch to ld/st_{be,le}_p() methods.
Signed-off-by: Philippe Mathieu-Daudé
---
TODO: Update docstring regexp
---
include/qemu/bswap.h | 19 +++
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