Grouping (GICv2) and Security Extensions change the behaviour of reads
of the highest priority pending interrupt register (ICCHPIR/GICC_HPPIR).
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc/arm_gic.c | 29 -
hw/intc/gic_internal.h | 1 +
2 files
Connect FIQ output of the GIC CPU interfaces to the CPUs.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/arm/vexpress.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index a88732c..bafe8d2 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
GICs with grouping (GICv2 or GICv1 with Security Extensions) have a
different exception generation model which is more complicated than
without interrupt grouping. We add a new function to handle this model.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc/arm_gic.c | 87
Fabian Aggeler (15):
hw/intc/arm_gic: Request FIQ sources
hw/arm/vexpress.c: Wire FIQ between CPU GIC
hw/intc/arm_gic: Add Security Extensions property
hw/intc/arm_gic: Add ns_access() function
hw/intc/arm_gic: Add Interrupt Group Registers
hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked
This register is banked in GICs with Security Extensions. Storing the
non-secure copy of BPR in the abpr, which is an alias to the non-secure
copy for secure access. ABPR itself is only accessible from secure state
if the GIC implements Security Extensions.
Signed-off-by: Fabian Aggeler aggel
For GICs with Security Extensions Non-secure reads have a restricted
view on the current running priority.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc/arm_gic.c | 17 -
hw/intc/gic_internal.h | 1 +
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git
-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc/arm_gic.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 75b5121..9b83af0 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -45,6 +45,13 @@ static inline int gic_get_current_cpu(GICState *s
.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc/arm_gic.c| 47 +---
hw/intc/arm_gic_common.c | 1 +
hw/intc/gic_internal.h | 4
include/hw/intc/arm_gic_common.h | 1 +
4 files changed, 50 insertions(+), 3
. Since this bit (Enable
Non-secure) is present in the integrated IC of the Cortex-A9 MPCore,
which implements the GICv1 profile, we support this bit in GICv1 too.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc/arm_gic.c| 34 ++
hw/intc
Grouping (GICv2) and Security Extensions change the behavior of IAR
reads. Acknowledging Group0 interrupts is only allowed from Secure
state and acknowledging Group1 interrupts from Secure state is only
allowed if AckCtl bit is set.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc
Grouping (GICv2) and Security Extensions change the behavior of EOIR
writes. Completing Group0 interrupts is only allowed from Secure state
and completing Group1 interrupts from Secure state is only allowed if
AckCtl bit is set.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc
GICs with Security Extensions restrict the non-secure view of the
interrupt priority and priority mask registers.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc/arm_gic.c | 66 +-
hw/intc/gic_internal.h | 3 +++
2 files changed
bits like AckCtl and FIQEn by changing
the type from bool to uint32. Since the field does not only store the
enable bit anymore and since we are touching the vmstate, we use the
opportunity to rename the field to cpu_control.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc/arm_gic.c
Preparing for FIQ lines from GIC to CPUs, which is needed for GIC
Security Extensions.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc/arm_gic.c| 3 +++
include/hw/intc/arm_gic_common.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc
for GICs which implement
Security Extensions.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc/arm_gic.c| 5 -
hw/intc/arm_gic_common.c | 1 +
include/hw/intc/arm_gic_common.h | 1 +
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b
Prepare to split gic_update() in two functions, one for GICs with
interrupt grouping and one without grouping (existing).
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/intc/arm_gic.c | 11 ---
hw/intc/gic_internal.h | 1 +
2 files changed, 9 insertions(+), 3 deletions
register (SCCTRL) to TIMCLK (1).
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/arm/vexpress.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index a88732c..086f68a 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
/archive/html/qemu-devel/2014-08/msg00629.html
v1 - v2:
* TIMERENXSEL prefixed with register name
* removed casts
* created header file
v1: https://lists.nongnu.org/archive/html/qemu-devel/2014-07/msg02572.html
Fabian Aggeler (2):
hw/misc/arm_sp810: Create SP810 device
hw/arm/vexpress: add SP810
This adds a device model for the PrimeXsys System Controller (SP810)
which is present in the Versatile Express motherboards. It is
so far read-only but allows to read the SCCTRL register.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
default-configs/arm-softmmu.mak | 1 +
hw/misc
register (SCCTRL) to TIMCLK (1).
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/arm/vexpress.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index a88732c..0b6d31a 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -34,6 +34,7
Fabian Aggeler (2):
hw/misc/arm_sp810: Create SP810 device
hw/arm/vexpress: add SP810 to the vexpress
default-configs/arm-softmmu.mak | 1 +
hw/arm/vexpress.c | 6 ++-
hw/misc/Makefile.objs | 1 +
hw/misc/arm_sp810.c | 98
This adds a device model for the PrimeXsys System Controller (SP810)
which is present in the Versatile Express motherboards. It is
so far read-only but allows to set the SCCTRL register.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
default-configs/arm-softmmu.mak | 1 +
hw/misc
the SCCTRL
register so that software that queries this register behaves
as expected.
Feedback is greatly appreciated!
Best,
Fabian
Fabian Aggeler (2):
hw/misc/arm_sp810: Create SP810 device
hw/arm/vexpress: add SP810 to the vexpress
default-configs/arm-softmmu.mak | 1 +
hw/arm/vexpress.c
This adds a device model for the PrimeXsys System Controller (SP810)
which is present in the Versatile Express motherboards. It is
so far read-only but allows to set the SCCTRL register.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
default-configs/arm-softmmu.mak | 1 +
hw/misc
register (SCCTRL) to TIMCLK (1).
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/arm/vexpress.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index a88732c..b96c3fd 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
Extensions).
Bits PD0/PD1 are now respected in get_phys_addr_v6/v5() and
get_level1_table_address.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
v2 - v3
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index cd7a5df..bd581e6 100644
--- a/target-arm/cpu.c
+++ b
* extended arm_is_secure() with EL3 handling
* rewrote nsacr patch
* removed MMU split for secure/nonsecure world
* removed arm_current_sctlr
* new banking scheme
v2: http://lists.gnu.org/archive/html/qemu-devel/2014-05/msg02522.html
Thanks,
Fabian
Fabian Aggeler (29):
target-arm: add cpu feature
If EL3 is using Aarch64 IRQ/FIQ masking is ignored in
all exception levels other than EL3 if SCR.{FIQ|IRQ} is
set to 1 (routed to EL3).
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 98 +---
1 file changed, 72 insertions
CPU
security state. It also allows to generate different TCG code depending on
CPU secure state.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 10 ++
target-arm/translate-a64.c | 1 +
target-arm
Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank
index 7).
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 4 ++--
target-arm/machine.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
Define a new ARM CP register info list for the ARMv7 Security Extension
feature. Register that list only for ARM cores with Security Extension/EL3
support. Moving Aarch32 SCR into Security Extension register group.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 15 +--
2 files changed, 10
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/helper.c | 9 +
1
to the Aarch64 EL register.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 35 +++
1 file changed, 35 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 221b847..0b8042c
From: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index
Implements NSACR register with corresponding read/write functions
for ARMv7 and ARMv8.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 6 +
target-arm/helper.c | 68
Make arm_current_pl() return PL3 for secure PL1 and monitor mode.
Increase MMU modes since mmu_index is directly infered from arm_
current_pl(). Changes assertion in arm_el_is_aa64() to allow EL3.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 15 +--
1 file
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/helper.c | 24 ++--
1 file changed, 6 insertions(+), 18 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8333b52..b9b458e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
arm_is_secure() function allows to determine CPU security state
if the CPU implements Security Extensions/EL3.
arm_is_secure_below_el3() returns true if CPU is in secure state
below EL3.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target
Implements SCTLR_EL3 and uses secure/non-secure instance when
needed.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/arm/pxa2xx.c| 2 +-
target-arm/cpu.c | 5 ++--
target-arm/cpu.h | 13 -
target-arm/helper.c| 78
Rename CSSELR (cache size selection register) and add secure
instance (Aarch32).
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 10 +-
target-arm/helper.c | 9 +
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/target-arm/cpu.h b/target
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
DACR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/arm/pxa2xx.c | 2 +-
target-arm/cpu.h| 13 +++--
target-arm/helper.c | 19 +++
3 files changed
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 13 -
target-arm/helper-a64.c | 17 ++---
target-arm/helper.c | 15
Add TTBR0 and maps secure/non-secure instance of ttbr0 and ttbr1
accordingly (translation table base register).
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 21 +++--
target-arm/helper.c | 45 +++--
2 files
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
and a non-secure instance.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 45 -
target-arm
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 10 +-
target-arm/helper.c | 9 +
2 files changed, 14 insertions(+), 5 deletions(-)
diff
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
Conflicts:
target-arm/helper.c
---
target-arm/cpu.c| 2 +-
target-arm/cpu.h| 21
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
PAR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 10 +-
target-arm/helper.c | 25 ++---
2 files changed, 23 insertions(+), 12
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
VBAR has a secure and a non-secure instance, which are mapped to
VBAR_EL1 and VBAR_EL3.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 12 +++-
target-arm/helper-a64.c | 6 +-
target-arm
Adds TCR_EL3 system register and makes existing TTBCR banked. Adjust
translation functions to use TCR/TTBCR instance depending on CPU state.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 11 ++-
target-arm/helper.c | 46
Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This
avoids recalculating them on switches from secure to non-secure world.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 10 --
target-arm/helper.c | 19 ---
2 files changed, 20
Adds a dedicated function for IRQ and FIQ exceptions to determine
target_el and mode (Aarch32) according to tables in ARM ARMv8 and
ARM ARM v7.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 3 ++
target-arm/helper.c | 137
Implements SMC instruction in Aarch32 using the A32 syndrome. When executing
SMC instruction from monitor CPU mode SCR.NS bit is reset.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/helper.c| 11 +++
target-arm
This patch extends arm_excp_unmasked() according to ARM ARMv7 and
ARM ARMv8 (all EL running in Aarch32) and adds comments.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 77
1 file changed, 61 insertions(+), 16
bits when modifying CPSR.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/helper.c | 42 +++---
1 file changed, 39 insertions(+), 3 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2fbecfa..f6ff4aa 100644
--- a/target
Prepare for cp register banking by inserting every cp register twice,
once for secure world and once for non-secure world.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 14 +++---
target-arm/helper.c| 20
target-arm/translate.c | 19
From: Sergey Fedorov s.fedo...@samsung.com
...from non-secure state.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index
Prepare ARMCPRegInfo to support specifying two fieldoffsets per
register definition. This will allow us to keep one register
definition for banked registers (different offsets for secure/
non-secure world).
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 16
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
v1 - v2:
* corrected typo (wich which)
* rebased
v1: http://lists.gnu.org/archive/html/qemu-devel/2014-05/msg03415.html
target-arm/helper.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target-arm
Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
Extensions).
Bits PD0/PD1 are now respected in get_phys_addr_v6/v5() and
get_level1_table_address.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
v1 - v2
to be zero anymore.
Bits PD0/PD1 are now respected in get_phys_addr_lpae() and
get_phys_addr_v6/v5().
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
Parts of this patch were previously part of the TZ patchset but
were rewritten to include ARMv8 RES0 and PD0/PD1 handling.
target-arm/cpu.h
ARM ARM v7 specifies SBOP/SBZP bits for v5/v6/v7. This patch
sets these bits on every sctlr_write(). In ARMv8 most of them are
RES0/RES1.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
Previously part of TZ patchset but now includes handling for SBOP/SBZP
bits in ARMv5/v6/v7. Not sure whether
implement a trace
macrocell nor a CP14 interface to the trace macrocell registers.
Since CPACR bits for VFP/Neon access are honoured with the CPACR_FPEN
bit in the TB flags, flushing the TLB is not necessary anymore.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
v1 - v2:
* Removed unnecessary
-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
This patch was previously part of the Security Extensions patchset and
got separated because it is not Sec-Ext specific.
In addition to a style fix of the comment I added qemu_log_mask() as
suggested
This patch changes some readfns/writefns to use raw_write
and raw_read functions, wich use the fieldoffset specified
in ARMCPRegInfo instead of directly accessing the field.
This will simplify patches for EL3 Security Extensions.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
This patch
On 14/05/14 20:39, Fedorov Sergey wrote:
14.05.2014 10:06, Sergey Fedorov пишет:
On 13.05.2014 20:15, Fabian Aggeler wrote:
From: Sergey Fedorov s.fedo...@samsung.com
CPACR register allows to control access rights to coprocessor 0-13
interfaces. Bits corresponding to unimplemented
From: Svetlana Fedoseeva s.fedose...@samsung.com
Define Security Extensions CPU feature. Set that feature for relevant CPUs.
Signed-off-by: Svetlana Fedoseeva s.fedose...@samsung.com
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target
From: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/helper.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3be917c..7898f40 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -768,9 +768,6
From: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c1388eb..cf1f88c 100644
SCR.{IRQ/FIQ} bits allows to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 2 ++
target-arm
...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 121 +
target-arm/helper.c| 64 --
target-arm/translate.c | 19 +---
3 files changed, 184 insertions(+), 20 deletions(-)
diff --git
This behaviour can be changed after all needed Aarch64 (_EL3)
registers are implemented and respected at locations where
behaviour is different when EL3 is in Aarch64 state.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 9 ++---
1 file changed, 6 insertions(+), 3
Add SCTLR_EL3 and introduce new function to access correct
instance of SCTLR in different modes/worlds.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
hw/arm/pxa2xx.c| 2 +-
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 4 +--
target-arm/cpu.h | 14
-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 7 ---
target-arm/helper.c| 2 ++
target-arm/machine.c | 6 +++---
target-arm/translate.c | 2 +-
4 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5eba825..a56d3d6 100644
-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/helper.c| 6 ++
target-arm/translate.c | 26 +++---
2 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index
arm_is_secure() function allows to determine CPU security state
if the CPU implements Security Extensions.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 15 +++
1 file changed, 15 insertions(+)
diff --git
() and MEM_INDEX_USER() macros instead.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 42 +++-
target-arm/helper.c| 2 +-
target-arm/translate-a64.c | 9 +-
target-arm/translate.c | 247
This way less case distinctions are necessary for different modes/worlds
as the reginfos already point at the correct offset.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/helper.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git
registers using A32_BANKED_REG_GET macro or
A32_MAPPED_EL3_REG_GET for registers which we map to EL3 registers.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
linux-user/main.c | 2 +-
target-arm/cpu.h| 32 ++
target
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 12 +++-
2 files changed, 8 insertions
bits when modifying CPSR.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 2 ++
target-arm/helper.c | 41 ++---
2 files changed, 40 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 212cb64..5de0c77
with the recent effort towards EL3
in A64.
Thanks,
Fabian
Fabian Aggeler (12):
target-arm: add arm_is_secure() function
target-arm: add NSACR support
target-arm: Split TLB for secure state and EL3 in Aarch64
target-arm: add banked coprocessor register type and macros
target-arm
From: Sergey Fedorov s.fedo...@samsung.com
TTBCR has additional fields PD0 and PD1 when using Short-descriptor
translation table format on a CPU with Security Extension support.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm
From: Sergey Fedorov s.fedo...@samsung.com
Make arm_current_pl() return PL3 for secure PL1 and monitor mode.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff
NSACR allows to control non-secure access to coprocessor interfaces 0-13
and CPACR bits.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 1 +
target-arm/helper.c| 29 +
target-arm
Some of SCTRL bits are common for secure and non-secure state.
Translation table base masks are updated on NS-bit switch as
well as on TTBCR writes.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h| 10 ++
target
From: Sergey Fedorov s.fedo...@samsung.com
SMC instruction is implemented similar to SVC instruction. When
executing SMC instruction from monitor CPU mode SCR.NS bit is reset.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h
From: Svetlana Fedoseeva s.fedose...@samsung.com
Signed-off-by: Svetlana Fedoseeva s.fedose...@samsung.com
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target
secure state. It also allows to generate different TCG code depending on
CPU secure state.
Signed-off-by: Sergey Fedorov s.fedo...@samsung.com
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
target-arm/cpu.h | 7 +++
target-arm/translate.c | 3 +++
target-arm/translate.h | 1 +
3 files
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