[PATCH v2] disas/riscv: Add decode for Zawrs extension

From: Balaji Ravikumar Add disassembly support for these instructions from Zawrs: * wrs.sto * wrs.nto Signed-off-by: Balaji Ravikumar Signed-off-by: Rob Bradford --- disas/riscv.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 05b663ebfe

[PATCH] disas/riscv: Add decode for Zawrs extension

From: Balaji Ravikumar Add disassembly support for these instructions from Zawrs: * wrs.sto * wrs.nto Signed-off-by: Balaji Ravikumar Signed-off-by: Rob Bradford --- disas/riscv.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 90d6b26de9

[PATCH v2] target/riscv: Remove experimental prefix from "B" extension

This extension has now been ratified: https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be removed. Since this is now a ratified extension add it to the list of extensions included in the "max" CPU variant. Signed-off-by: Rob Bradford Reviewed-by: Andrew Jone

[PATCH] target/riscv: Remove experimental prefix from "B" extension

This extension has now been ratified: https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be removed. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PATCH v3 3/3] target/riscv: Expose Zaamo and Zalrsc extensions

Expose the newly added extensions to the guest and allow their control through the CPU properties. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8d3ec74a1c..604baf53c8 100644 --- a/target

[PATCH v3 2/3] target/riscv: Check 'A' and split extensions for atomic instructions

Following the pattern for 'M' and Zmmul check if either the 'A' extension is enabled or the appropriate split extension for the instruction. Signed-off-by: Rob Bradford --- target/riscv/insn_trans/trans_rva.c.inc | 56 +++-- 1 file changed, 34 insertions(+), 22 deletions

[PATCH v3 1/3] target/riscv: Add Zaamo and Zalrsc extension infrastructure

These extensions represent the atomic operations from A (Zaamo) and the Load-Reserved/Store-Conditional operations from A (Zalrsc) Signed-off-by: Rob Bradford Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu_cfg.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv

[PATCH v3 0/3] target/riscv: Add support for Zaamo & Zalrsc

mpatibility enabling the A instruction does not enable these two extensions - future hardware may choose to advertise support for A and both these extensions for maximum software support. This patch is based off riscv-to-apply.next due to conflicts with existing patches. Cheers, Rob [1] - https://gi

[PATCH v2 1/2] target/riscv: Add Zaamo and Zalrsc extensions

These extensions represent the atomic operations from A (Zaamo) and the Load-Reserved/Store-Conditional operations from A (Zalrsc) Signed-off-by: Rob Bradford Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 5 + target/riscv/cpu_cfg.h | 2 ++ 2 files changed, 7 insertions

[PATCH v2 0/2] target/riscv: Add support for Zaamo & Zalrsc

mpatibility enabling the A instruction does not enable these two extensions - future hardware may choose to advertise support for A and both these extensions for maximum software support. This patch is based off riscv-to-apply.next due to conflicts with existing patches. Cheers, Rob [1] - https://gi

[PATCH v2 2/2] target/riscv: Check 'A' and split extensions for atomic instructions

Following the pattern for 'M' and Zmmul check if either the 'A' extension is enabled or the appropriate split extension for the instruction. Signed-off-by: Rob Bradford --- target/riscv/insn_trans/trans_rva.c.inc | 56 +++-- 1 file changed, 34 insertions(+), 22 deletions

Re: [PATCH 2/2] target/riscv: Check 'A' and split extensions for atomic instructions

On Thu, 2024-01-18 at 16:49 -0300, Daniel Henrique Barboza wrote: > > > On 1/15/24 13:25, Rob Bradford wrote: > > Following the pattern for 'M' and Zmmul check if either the 'A' > > extension is enabled or the appropriate split extension for the > > instru

[PATCH 2/2] target/riscv: Check 'A' and split extensions for atomic instructions

Following the pattern for 'M' and Zmmul check if either the 'A' extension is enabled or the appropriate split extension for the instruction. Also remove the assumption that only checking for 64-bit systems is required for the double word variants. Signed-off-by: Rob Bradford --- target/riscv

[PATCH 1/2] target/riscv: Add Zaamo and Zalrsc extensions

These extensions represent the atomic operations from A (Zaamo) and the Load-Reserved/Store-Conditional operations from A (Zalrsc) Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 5 + target/riscv/cpu_cfg.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b

[PATCH 0/2] target/riscv: Add support for Zaamo & Zalrsc

mpatibility enabling the A instruction does not enable these two extensions - future hardware may choose to advertise support for A and both these extensions for maximum software support. This patch is based off riscv-to-apply.next due to conflicts with existing patches. Cheers, Rob [1] - https://gi

Re: Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension

On Fri, 2024-01-12 at 17:08 +0100, Andrew Jones wrote: > On Thu, Jan 11, 2024 at 03:17:25PM +0000, Rob Bradford wrote: > > + Ved > > > > On Thu, 2024-01-11 at 14:14 +0100, Andrew Jones wrote: > > > On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote: > &g

Re: [PATCH 0/2] Export debug triggers as an extension

ification should freeze this month. How about considering this as a solution: - Add a new x-sdtrig option that defaults to false - Deprecate debug option - but retain it with default on - Add warning if triggers are used and x-sdtrig is not enabled - Update the trigger implementation to match frozen spec There is potentially a chance that some use cases will be broken but I don't think triggers are being widely use - the SBI support only just got merged: https://github.com/riscv-software-src/opensbi/commit/97f234f15c9657c6ec69fa6ed745be8107bf6ae2 Hope this is helpful, Rob

[PATCH v2 1/2] target/riscv: Add infrastructure for 'B' MISA extension

Add the infrastructure for the 'B' extension which is the union of the Zba, Zbb and Zbs instructions. Signed-off-by: Rob Bradford Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu.h | 1 + target/riscv/tcg/tcg

[PATCH v2 0/2] target/riscv: Add support for 'B' extension

is not enabled by default in any cpu. Cheers, Rob [1] - https://github.com/riscv/riscv-b Changes since V1: - Rebased on master after latest riscv updates - All patches have R-B tags - Array formatting fix to make future diffs clean (Daniel) - Dropped enabling for max CPU variant as misa.B is reserved

[PATCH v2 2/2] target/riscv: Add step to validate 'B' extension

If the B extension is enabled warn if the user has disabled any of the required extensions that are part of the 'B' extension. Conversely enable the extensions that make up the 'B' extension if it is enabled. Signed-off-by: Rob Bradford Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew

Re: [PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type

On Thu, 2024-01-11 at 11:53 -0300, Daniel Henrique Barboza wrote: > > > On 1/11/24 10:02, Andrew Jones wrote: > > On Wed, Jan 10, 2024 at 03:32:21PM -0300, Daniel Henrique Barboza > > wrote: > > > > > > > > > On 1/9/24 14:07, Rob Bra

Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension

+ Ved On Thu, 2024-01-11 at 14:14 +0100, Andrew Jones wrote: > On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote: > > On Tue, Jan 09, 2024 at 05:07:35PM +, Rob Bradford wrote: > > > Add the infrastructure for the 'B' extension which is the union > > > of

[PATCH] target/riscv: Check for 'A' extension on all atomic instructions

Add requirement that 'A' is enabled for all atomic instructions that lack the check. This makes the 64-bit versions consistent with the 32-bit versions in the same file. Signed-off-by: Rob Bradford --- target/riscv/insn_trans/trans_rva.c.inc | 11 +++ 1 file changed, 11 insertions

[PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension

Add the infrastructure for the 'B' extension which is the union of the Zba, Zbb and Zbs instructions. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 1 + 3 files changed, 5 insertions(+), 2 deletions(-) diff

[PATCH 2/3] target/riscv: Add step to validate 'B' extension

If the B extension is enabled warn if the user has disabled any of the required extensions that are part of the 'B' extension. Conversely enable the extensions that make up the 'B' extension if it is enabled. Signed-off-by: Rob Bradford --- target/riscv/tcg/tcg-cpu.c | 33

[PATCH 0/3] target/riscv: Add support for 'B' extension

is not enabled by default in any cpu other than the 'max' variant. Cheers, Rob [1] - https://github.com/riscv/riscv-b [2] - https://patchew.org/QEMU/20231218125334.37184-1-dbarb...@ventanamicro.com/20231218125334.37184-16-dbarb...@ventanamicro.com/ Rob Bradford (3): target/riscv: Add

[PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type

Signed-off-by: Rob Bradford --- target/riscv/tcg/tcg-cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f10871d352..9705daec93 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -999,7

Re: [PATCH 1/2] target/riscv: Add support for Zacas extension

Hi Alistair, Thanks for providing some feedback - responses below: On Mon, 2023-12-18 at 12:54 +1000, Alistair Francis wrote: > On Fri, Dec 8, 2023 at 1:40 AM Rob Bradford > wrote: > > > > From: Weiwei Li > > > > Add support for amocas.w/d/q instructions whic

[PATCH 1/2] target/riscv: Add support for Zacas extension

From: Weiwei Li Add support for amocas.w/d/q instructions which are part of the ratified Zacas extension: https://github.com/riscv/riscv-zacas Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 2 + target

[PATCH 2/2] disas/riscv: Add amocas.[w,d,q] instructions

Signed-off-by: Rob Bradford --- disas/riscv.c | 9 + 1 file changed, 9 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index e9458e574b..8a546d5ea5 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -903,6 +903,9 @@ typedef enum { rv_op_vwsll_vv = 872, rv_op_vwsll_vx

[PATCH 0/2] Add support for (ratified) Zacas extension

iscv-software-src/riscv-tests/pull/492 Rob Bradford (1): disas/riscv: Add amocas.[w,d,q] instructions Weiwei Li (1): target/riscv: Add support for Zacas extension disas/riscv.c | 9 ++ target/riscv/cpu.c | 2 + target/riscv/cpu_c

Re: [PATCH v4 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num"

On Mon, 2023-10-23 at 12:02 +1000, Alistair Francis wrote: > On Thu, Oct 19, 2023 at 1:45 AM Rob Bradford > wrote: > > > > Using a mask instead of the number of PMU devices supports the > > accurate > > emulation of platforms that have a discontinuous set of PMU &

[PATCH v5 4/5] target/riscv: Add "pmu-mask" property to replace "pmu-num"

e order on the command line determines which takes precedence (later overwriting earlier.) Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 40 +- target/riscv/cpu_cfg.h | 2 +- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 15 +++

[PATCH v5 5/5] docs/about/deprecated: Document RISC-V "pmu-num" deprecation

This has been replaced by a "pmu-mask" property that provides much more flexibility. Signed-off-by: Rob Bradford Acked-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- docs/about/deprecated.rst | 12 1 file changed, 12 insertions(+) diff --

[PATCH v5 3/5] target/riscv: Use existing PMU counter mask in FDT generation

During the FDT generation use the existing mask containing the enabled counters rather then generating a new one. Using the existing mask will support the use of discontinuous counters. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Atish Patra

[PATCH v5 1/5] target/riscv: Propagate error from PMU setup

More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford Reviewed-by: Alistair

[PATCH v5 2/5] target/riscv: Don't assume PMU counters are continuous

Check the PMU available bitmask when checking if a counter is valid rather than comparing the index against the number of PMUs. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- target/riscv/csr.c | 5 +++-- 1 file changed, 3

[PATCH v5 0/5] Support discontinuous PMU counters

f MAKE_32BIT_MASK() v2: * Use cfg.pmu_mask wherever cfg.pmu_num was used previously * Deprecate pmu_num property (warning, comment & updated documentation) * Override default pmu_mask value iff pmu_num changed from default Rob Bradford (5): target/riscv: Propagate error from PMU setup targe

[PATCH v4 5/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation

This has been replaced by a "pmu-mask" property that provides much more flexibility. Signed-off-by: Rob Bradford Acked-by: LIU Zhiwei --- docs/about/deprecated.rst | 12 1 file changed, 12 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated

[PATCH v4 6/6] target/riscv: Use MAKE_64BIT_MASK instead of custom macro

A 32-bit mask can be trivially created using the 64-bit macro so make use of that instead. Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis --- target/riscv/pmu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index

[PATCH v4 1/6] target/riscv: Propagate error from PMU setup

More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford Reviewed-by: Alistair

[PATCH v4 2/6] target/riscv: Don't assume PMU counters are continuous

Check the PMU available bitmask when checking if a counter is valid rather than comparing the index against the number of PMUs. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions

[PATCH v4 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num"

e property is not explicitly by the user the property default value cannot be used so the default value must be set during the CPU object initialisation. If the "pmu-num" value is changed from the default then the mask will be generated from that to support the transition to "pmu-m

[PATCH v4 0/6] Support discontinuous PMU counters

dated documentation) * Override default pmu_mask value iff pmu_num changed from default Rob Bradford (6): target/riscv: Propagate error from PMU setup target/riscv: Don't assume PMU counters are continuous target/riscv: Use existing PMU counter mask in FDT generation target/riscv: Add "

[PATCH v4 3/6] target/riscv: Use existing PMU counter mask in FDT generation

During the FDT generation use the existing mask containing the enabled counters rather then generating a new one. Using the existing mask will support the use of discontinuous counters. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- hw/riscv/virt.c

[PATCH v3 1/6] target/riscv: Propagate error from PMU setup

More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford Reviewed-by: Alistair

[PATCH v3 6/6] target/riscv: Use MAKE_64BIT_MASK instead of custom macro

A 32-bit mask can be trivially created using the 64-bit macro so make use of that instead. Signed-off-by: Rob Bradford --- target/riscv/pmu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 9253e5f17a..052d5b1164 100644

[PATCH v3 5/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation

This has been replaced by a "pmu-mask" property that provides much more flexibility. Signed-off-by: Rob Bradford Acked-by: LIU Zhiwei --- docs/about/deprecated.rst | 10 ++ 1 file changed, 10 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated

[PATCH v3 2/6] target/riscv: Don't assume PMU counters are continuous

Check the PMU available bitmask when checking if a counter is valid rather than comparing the index against the number of PMUs. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei --- target/riscv/csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c

[PATCH v3 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num"

the default Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu_cfg.h | 3 ++- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 20 4 files changed, 22 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PATCH v3 0/6] Support discontinuous PMU counters

previously * Deprecate pmu_num property (warning, comment & updated documentation) * Override default pmu_mask value iff pmu_num changed from default Rob Bradford (6): target/riscv: Propagate error from PMU setup target/riscv: Don't assume PMU counters are continuous target/riscv: Us

[PATCH v3 3/6] target/riscv: Use existing PMU counter mask in FDT generation

During the FDT generation use the existing mask containing the enabled counters rather then generating a new one. Using the existing mask will support the use of discontinuous counters. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei --- hw/riscv/virt.c| 2 +- target/riscv/pmu.c | 6

Re: [PATCH v2 5/6] target/riscv: Add "pmu-mask" property to replace "pmu-num"

On Thu, 2023-10-12 at 17:05 +0800, LIU Zhiwei wrote: >   > >   >   > On 2023/10/11 22:45, Rob Bradford wrote: >   >   > >   > > Using a mask instead of the number of PMU devices supports the > > accurate > > emulation of platforms that

[PATCH v2 2/6] target/riscv: Don't assume PMU counters are continuous

Check the PMU available bitmask when checking if a counter is valid rather than comparing the index against the number of PMUs. Signed-off-by: Rob Bradford --- target/riscv/csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c

[PATCH v2 0/6] Support discontinuous PMU counters

ers though a "pmu-mask" property. v2: * Use cfg.pmu_mask wherever cfg.pmu_num was used previously * Deprecate pmu_num property (warning, comment & updated documentation) * Override default pmu_mask value iff pmu_num changed from default Rob Bradford (6): target/riscv: Propag

[PATCH v2 6/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation

This has been replaced by a "pmu-mask" property that provides much more flexibility. Signed-off-by: Rob Bradford --- docs/about/deprecated.rst | 10 ++ 1 file changed, 10 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 8b136320e2..

[PATCH v2 3/6] target/riscv: Use existing PMU counter mask in FDT generation

During the FDT generation use the existing mask containing the enabled counters rather then generating a new one. Using the existing mask will support the use of discontinuous counters. Signed-off-by: Rob Bradford --- hw/riscv/virt.c| 2 +- target/riscv/pmu.c | 6 +- target/riscv/pmu.h

[PATCH v2 5/6] target/riscv: Add "pmu-mask" property to replace "pmu-num"

the default Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu_cfg.h | 3 ++- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 14 ++ 4 files changed, 16 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PATCH v2 4/6] qemu/bitops.h: Add MAKE_32BIT_MASK macro

Add 32-bit version of mask generating macro and use it in the RISC-V PMU code. Signed-off-by: Rob Bradford --- include/qemu/bitops.h | 3 +++ target/riscv/pmu.c| 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index

[PATCH v2 1/6] target/riscv: Propagate error from PMU setup

More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford Reviewed-by: Alistair

Re: [PATCH 2/3] target/riscv: Support discontinuous PMU counters

On Mon, 2023-10-09 at 11:00 -0700, Atish Kumar Patra wrote: > On Sun, Oct 8, 2023 at 5:58 PM Alistair Francis > wrote: > > > > On Wed, Oct 4, 2023 at 7:36 PM Rob Bradford > > wrote: > > > > > > Hi Atish, > > > > > > On Tue, 2023-1

Re: [PATCH 2/3] target/riscv: Support discontinuous PMU counters

Hi Atish, On Tue, 2023-10-03 at 13:25 -0700, Atish Kumar Patra wrote: > On Tue, Oct 3, 2023 at 5:51 AM Rob Bradford > wrote: > > > > There is no requirement that the enabled counters in the platform > > are > > continuously numbered. Add a "pmu-mask&qu

[PATCH 3/3] target/riscv: Don't assume PMU counters are continuous

Check the PMU available bitmask when checking if a counter is valid rather than comparing the index against the number of PMUs. Signed-off-by: Rob Bradford --- target/riscv/csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c

[PATCH 1/3] target/riscv: Propagate error from PMU setup

More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford --- target/riscv/cpu.c

[PATCH 2/3] target/riscv: Support discontinuous PMU counters

o match the number of bits set in the mask. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/pmu.c | 15 +-- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9d79c20c1a..

[PATCH 0/3] Support discontinuous PMU counters

ers though a "pmu-mask" property. Rob Bradford (3): target/riscv: Propagate error from PMU setup target/riscv: Support discontinuous PMU counters target/riscv: Don't assume PMU counters are continuous target/riscv/cpu.c | 9 - target/riscv/cpu_cfg.h | 1 + target/

[PATCH] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren

max value to these CSRs and upon subsequent read the appropriate number of bits for number of PMUs is enabled and the TM bit is zero in mcountinhibit. Signed-off-by: Rob Bradford --- target/riscv/csr.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/riscv

[PATCH v2] target/riscv: Fix LMUL check to use VLEN

1/8 must be supported." Elsewhere in the specification it makes clear that VLEN>=ELEN. >From inspection this new check allows: VLEN=ELEN=64 1/2, 1/4, 1/8 for SEW >=8 VLEN=ELEN=32 1/2, 1/4 for SEW >=8 Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions")

Re: [PATCH] target/riscv: Fix LMUL check to use minimum SEW

On Thu, 2023-07-06 at 21:22 +0800, Weiwei Li wrote: > > On 2023/7/6 18:44, Rob Bradford wrote: > > The previous check was failing with: > > > > ELEN = 64 SEW = 16 and LMUL = 1/8 (encoded as 5) which is a valid > > combination. > > > > Fix the check to

[PATCH] target/riscv: Fix LMUL check to use minimum SEW

al LMULs of 1/2, 1/4, and 1/8 must be supported." >From inspection this new check allows: ELEN=64 1/2, 1/4, 1/8 (encoded as 7, 6, 5 respectfully) ELEN=32 1/2, 1/4 (encoded as 7 and 6 respectfully) Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions") S

Re: [PATCH 1/2] target/riscv: Add Zacas ISA extension support

On Fri, 2023-06-02 at 23:04 +0800, Weiwei Li wrote: > > On 2023/6/2 20:16, Rob Bradford wrote: > > This commit adds support for the the amocas.{w,d,q} instructions > > behind > > a new property to enable that instruction. > > > > Signed-off-by: Rob Bradf

Re: [PATCH v2 1/6] target/riscv: Add properties for BF16 extensions

On Thu, 2023-06-15 at 21:14 +0800, Weiwei Li wrote: > > On 2023/6/15 20:58, Rob Bradford wrote: > > On Thu, 2023-06-15 at 14:32 +0800, Weiwei Li wrote: > > > Add ext_zfbfmin/zvfbfmin/zvfbfwma properties. > > > Add require check for BF16 extensions. > &g

Re: [PATCH v2 1/6] target/riscv: Add properties for BF16 extensions

he "V" extension or the Zve32f embedded vector extension." So this should be: +if (cpu->cfg.ext_zvfbfmin && !(cpu->cfg.ext_zve32f || cpu- >cfg.ext_v) { +error_setg(errp, "Zvfbfmin extension depends on Zve32f or V extension"); +return; +

Re: [PATCH 2/2] disas/riscv: Add support for amocas.{w, d, q} instructions

On Fri, 2 Jun 2023 at 13:17, Rob Bradford wrote: > /* structures */ > @@ -2123,6 +2126,9 @@ const rv_opcode_data opcode_data[] = { > { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, > { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL

[PATCH 2/2] disas/riscv: Add support for amocas.{w,d,q} instructions

Signed-off-by: Rob Bradford --- disas/riscv.c | 9 + 1 file changed, 9 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index d597161d46..dbed2010f8 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -964,6 +964,9 @@ typedef enum { rv_op_cm_jalt = 788, rv_op_czero_eqz

[PATCH 1/2] target/riscv: Add Zacas ISA extension support

This commit adds support for the the amocas.{w,d,q} instructions behind a new property to enable that instruction. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 4 + target/riscv/cpu.h | 1 + target/riscv/insn32.decode

RFC: target/riscv: Add support for Zacas extension

The Zacas[1] extension is a proposed unprivileged ISA extension for adding support for atomic compare-and-swap. Since this extension is not yet frozen (although no significant changes are expected) these patches are RFC/informational. Cheers, Rob [1] - https://github.com/riscv/riscv-zacas/blob

Re: [PATCH] hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR

On 3/29/23 12:23, Philippe Mathieu-Daudé wrote: > On 29/3/23 18:48, Rob Landley wrote: >>>> Works fine for me. Somebody said it was the wrong fix but I don't remember >>>> why... >>> >>> This is a correct /partial/ fix. With this patch, Malta works

Re: [PATCH] hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR

On 3/29/23 11:07, Philippe Mathieu-Daudé wrote: > On 29/3/23 18:09, Rob Landley wrote: >> On 3/28/23 12:02, Philippe Mathieu-Daudé wrote: >>> On 20/3/23 17:58, Nathan Chancellor wrote: >>>> On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote:

Re: [PATCH] hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR

t, which does a basic automated smoketest against all the support qemu images. https://github.com/landley/toybox/blob/master/scripts/test_mkroot.sh I also have a 300 line bash script that builds and packages all the Linux test systems from source (it's mkroot.sh in the same directory if you're wondering how to build a bootable Linux system for a dozen targets in 300 lines of bash, and it's documented at https://landley.net/toybox/faq.html#mkroot and that links to prebuilt binaries, and the instructions and scripts to build the cross compilers I use, and prebuilt binaries for those too... Anyway, tl;dr I both care and can regression test this easily, but haven't seen an agreed on "try this patch instead of the other patch" go by? (Might have missed it?) Rob

Re: [PATCH] hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR

On 3/28/23 12:02, Philippe Mathieu-Daudé wrote: > On 20/3/23 17:58, Nathan Chancellor wrote: >> On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote: >>> On 23/2/23 17:19, Jiaxun Yang wrote: 145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE

Re: Commit 145e2198d749 broke mips big endian.

On 1/21/23 07:14, Peter Maydell wrote: > On Sat, 21 Jan 2023 at 10:45, Rob Landley wrote: >> >> wget https://landley.net/toybox/downloads/binaries/mkroot/0.8.9/mips.tgz >> extract >> and ./run-qemu.sh in there. Before this commit it goes: > > Hi; does this pa

Commit 145e2198d749 broke mips big endian.

stered PF_INET6 protocol family Segment Routing with IPv6 Afterwards: loop: module loaded NET: Registered PF_INET6 protocol family Segment Routing with IPv6 and lots of hardware is missing. (I noticed ethernet first.) The mipsel.tgz in the same directory still worked. Rob

Re: [PATCH v2 5/8] hw/arm/virt: Fix devicetree warnings about the GPIO node

lled version too). That binding happens to be pretty lax and allows the GPIO to be specified either with 'gpios' or 'interrupts' property. The Linux PL061 driver happens to work only because it always registers an interrupt controller regardless of having "interrupt-controller" and "#interrupt-cells" properties or not. Rob

Re: [PATCH v2 4/8] hw/arm/virt: Fix devicetree warning about the gpio-key node

m to fix (in a few cases we do end up relaxing the schemas). On the flip side, even existing things eventually get updated for coding style or evolving conventions. As long as we don't break ABIs, the same should apply to DT. Rob

Re: [PATCH v2 8/8] hw/arm/virt: Fix devicetree warnings about node names

en no checking of them or many things for a long time, but now we can check much more than reviews ever could we have a huge technical debt. The main reason on care on these is just consistency. Rob [1] https://elinux.org/images/c/cf/Power_ePAPR_APPROVED_v1.1.pdf

Re: [PATCH v2 3/4] hw/riscv: virt: fix syscon subnode paths

t;> under {'type': 'object'} > >>From schema: > >> /home/conor/.local/lib/python3.9/site-packages/dtschema/schemas/simple-bus.yaml > >> /stuff/qemu/qemu.dtb: soc: reboot: {'value': [[30583]], 'offset': [[0]], > >> 'regmap': [[4]], 'compatible': ['sysc

Re: [PATCH v2] hw/arm: add versioning to sbsa-ref machine DT

On Tue, May 17, 2022 at 11:50 AM Peter Maydell wrote: > > On Tue, 17 May 2022 at 14:27, Rob Herring wrote: > > > > On Thu, May 5, 2022 at 6:41 AM Leif Lindholm > > wrote: > > > > > > The sbsa-ref machine is continuously evolving. Some of the change

Re: [PATCH v2] hw/arm: add versioning to sbsa-ref machine DT

On Thu, May 5, 2022 at 6:41 AM Leif Lindholm wrote: > > The sbsa-ref machine is continuously evolving. Some of the changes we > want to make in the near future, to align with real components (e.g. > the GIC-700), will break compatibility for existing firmware. > > Introduce two new properties to

Re: serial hang in qemu-system-ppc64 -M pseries

On 4/29/22 16:43, Fabiano Rosas wrote: > Rob Landley writes: >> Then paste something longer than 16 characters at the eventual command prompt >> once the kernel finishes booting. > > I suspect this is due to how the tty driver (n_tty.c) interacts with > the console

Re: serial hang in qemu-system-ppc64 -M pseries

On 4/28/22 00:41, Rob Landley wrote: > On 4/27/22 10:27, Thomas Huth wrote: >> On 26/04/2022 12.26, Rob Landley wrote: >>> When I cut and paste 80-ish characters of text into the Linux serial >>> console, it >>> reads 16 characters and stops. W

Re: serial hang in qemu-system-ppc64 -M pseries

On 4/27/22 10:27, Thomas Huth wrote: > On 26/04/2022 12.26, Rob Landley wrote: >> When I cut and paste 80-ish characters of text into the Linux serial >> console, it >> reads 16 characters and stops. When I hit space, it reads another 16 >> characters, >> an

serial hang in qemu-system-ppc64 -M pseries

-ppc64 -M pseries -vga none -nographic -no-reboot -m 256 -kernel vmlinux -initrd powerpc64leroot.cpio.gz -append "panic=1 HOST=powerpc64le console=hvc0" Rob linux-fullconfig.gz Description: application/gzip

Re: [PATCH 01/20] Hexagon HVX (target/hexagon) README

On 7/26/21 8:59 AM, Taylor Simpson wrote: > We're working on system mode support for Hexagon, and we plan to upstream it > when it is ready. > > Thanks, > Taylor Any progress on this? (Is there a way for outsiders to track the status?) Thanks, Rob

Re: [PATCH for-6.2 12/43] target/sh4: Implement do_unaligned_access for user-only

es but that target doesn't have unaligned interrupts yet. (I think it just masks off the bottom 2 bits to do the next lowest aligned access? It's an sh2 variant and the plumbing to let interrupts restart multi-clock instructions is only in the j32 branch so far, so the j2 and ice40 targets don't generate interrupts for it. Todo item, in the meantime we need to clean unaligned access out of application code so faulting on it is good.) > -- PMM Thanks, Rob

Re: [PATCH 01/20] Hexagon HVX (target/hexagon) README

t they just sizeof(void *) in a header file? *shrug* I can do the above trick in the wrapper script and then provide -DCMAKE_SIZEOF_VOID_P=$BLAH on the command line, it just seems DEEPLY pointless to go to all the trouble of having a ./configure that has to be manually told stuff the compiler already knows. Confused, Rob

Re: [PATCH 01/20] Hexagon HVX (target/hexagon) README

On 7/26/21 2:57 AM, Rob Landley wrote: > Anyway... it doesn't look like qemu-system-hexagon (softmmu) its currently in > vanilla qemu? Is there a public fork that has this somewhere? I did a little wild flailing to get ./configure to give me a qemu-system-hexagon option (patch attached

Re: [PATCH 01/20] Hexagon HVX (target/hexagon) README

On 7/19/21 11:19 AM, Sid Manning wrote:>> -Original Message- >> From: Brian Cain >> Sent: Monday, July 19, 2021 8:40 AM >> To: Rob Landley ; Taylor Simpson >> ; qemu-devel@nongnu.org; Sid Manning >> >> Cc: a...@rev.ng; peter.mayd...@linaro

Re: [PATCH 01/20] Hexagon HVX (target/hexagon) README

linux/commit/e0e2fa4b515c but checked again to be sure.) Presumably this is more "shared with full kernel build". And then build_musl, covered above under the headers build: lotsa flags, not sure why. > -Brian > Rob P.S. It took me a while to figure out that clang_rt is NOT libr

Re: [PATCH 01/20] Hexagon HVX (target/hexagon) README

mit it (to avoid building lld _twice_) will I (probably) get a working hexagon toolchain? (Assuming I do the musl and headers-install builds and so on?) What's the _issue_ here that this config symbol addresses? Thanks, Rob

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