7;t own one
and was in my concerns if I could actually write
code for it not too differently from what I already know...
Before I get one ;-)
Thanks, that was exactly the starter info I was looking.
Luis Cupido.
ct1dmk.
p.s. Many tks also to all the other replies.
On 1/23/2012 5:49 AM, J
Is it possible to program under Windows, still
using the old_style national instruments 'ib...' calls.
when using USB-GPIB interfaces like prologix or others ?
many tks.
Luis Cupido.
ct1dmk.
p.s.(I only have real GPIB 'c' programming experience on MSDOS
all the rest is us
names or extinct etc.
Any a light on the subject ?
(or has catalogs/manuals of such)
tks.
Luis Cupido.
ct1dmk
p.s. Also for "Kinetic Systems" and "LeCroy" it seems hard too
but I could find some stuff, but even so not what I wanted :-(
__
Just read this one...
I just wonder if I did anything that terrible in a past life to
deserve reading this ... ;-)
Recently on Microwaves and RF.
http://mwrf.com/Articles/ArticleID/23644/23644.html
lc.
ct1dmk.
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I had similar need some time ago and
I found that a differential pair with two (pnp) BFR93
worked much better than any comparator(three or four tested, but not the
adcmp604).
(was a pll reference and I judged the impact of such
observing the phase noise at microwaves).
lc.
ct1dmk.
On 9/9/201
Gerhard.
This was an old thing I asked a month ago or so...
Only the MSB of the accumulator is used to serve
as reference to a pll. No sin or DAC involved ;-)
Luis Cupido.
ct1dmk
On 7/21/2011 6:10 PM, dk...@arcor.de wrote:
IMHO, that would require a sine table with a steerable number
of
so far I did not caught the idea clearly enough to start
coding...)
Luis Cupido.
ct1dmk.
p.s. No problem with the delay... ;-)
On 7/21/2011 9:11 AM, Magnus Danielson wrote:
On 21/06/11 12:48, Luis Cupido wrote:
Yes that right. Is clear that I would have a 10ns jitter,
So the catch would be to
Thanks Jim,
Joseph already pointed me to a pdf in a previous post.
Now it is digestion time... should I say congestion !!!
those MASH delta-sigmas are killing me...
lc.
ct1dmk.
On 6/23/2011 4:30 AM, Jim Lux wrote:
On 6/22/11 3:36 PM, Luis Cupido wrote:
I knew I must not have been the fist
Indeed, may google be...
Thanks, Joseph.
lc
ct1dmk.
On 6/23/2011 12:12 AM, Joseph M Gwinn wrote:
May Google be with you: A search on the title and an author yielded:
<http://petrified.ucsd.edu/~ispg-adm/pubs/mtt-s_2006.pdf>
From: Luis Cupido
To: Discuss
I knew I must not have been the fist one to be looking for such.
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4014919
(unfortunately I'm not ieee member and $30 looks more like a
book price to me... not an article... bahhh!)
Luis Cupido.
ct1dmk.
On 6/21/2011 11:48 AM, Luis C
Hi Brent,
A quarter table cos is exactly the same as a quarter table sin.
Only backwards, and not telling which quarter it is makes it a
quarter of either sin or cos. For one single output becomes irrelevant
as you only need one.
So I think it is just a matter of taste the name to call it.
Luis
I've played with the core from altera for a while, but since I was only
interested in 1 bit I'm now playing with my own code. Trivial variations
on the plain old clocked accumulator architecture.
lc
On 6/21/2011 7:37 AM, Javier Herrero wrote:
What it the topology you're using now? Also, I wo
Yes that right. Is clear that I would have a 10ns jitter,
So the catch would be to find a scheme to spread spurs out or to push
them away from carrier. Then they would not bother me (would not pass
the PLL).
lc
ct1dmk.
On 6/21/2011 7:43 AM, Javier Herrero wrote:
But I forgot to add that t
first LO for an experiment in SDR radio
at VHF-SHF region,(not HF).
Luis Cupido.
ct1dmk.
On 6/21/2011 10:03 AM, Ulrich Bangert wrote:
Luis,
the information that you are concerned about close carrier spurs that will
pass through the PLL's low pass filter is not precise enough: are you
ta
the artifacts associated with output quantization are above
the desired carrier frequency. Sometimes the MSB's toggle
period is going to be shorter than it should be, and
sometimes it's going to be longer.
-- john, KE5FX
-Original Message-
From: time-nuts-boun...@febo.com [mailt
ssing required to be done after and producing a square wave).
Thanks for your patience.
Luis Cupido.
ct1dmk
P.S. At the moment I'm testing on the bench with a real FPGA cyclone III
with a 48bit dds at 100MHz fclock and at circa 6 and 18MHz output and it
is not that bad. I got better t
..
Anyone knows any literature covering that ?
Thanks.
Luis cupido.
ct1dmk.
On 6/20/2011 4:52 PM, Javier Herrero wrote:
To reduce the spurii due to quantization distortion. Here is an
explanation, in Section 4
http://www.analog.com/static/imported-files/tutorials/450968421DDS_Tutorial
Well, if we really need to filter it out
we better filter the MSB and square it
again...
Why having a DAC for ???
Right ?
Luis Cupido.
ct1dmk.
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e got to have nothing in
the alias region for it to be ok. (not my application
at the moment but will keep that in mind)
Thanks guys...
Luis Cupido.
ct1dmk.
On 6/20/2011 4:11 PM, Graham / KE9H wrote:
Luis:
No, not the same.
The most significant bit out of the accumulator has the
Forgot the sine table...
I meant obviously <...an accumulator 'sine table' and DAC...>
lc.
On 6/20/2011 3:46 PM, Luis Cupido wrote:
Folks, a quick one...
A DDS, that is an accumulator with a DAC followed by a low pass filter
and comparator (zero crossing) to produce a square
lator.
Or am I missing something here ?
Comments appreciated.
thanks.
Luis Cupido.
ct1dmk.
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have on a PLL.
All that may fall below most practical needs(1), I agree...
But in the timenuts spirit ought to be pointed out... right ? ;-)
Luis Cupido
ct1dmk.
p.s. (1) folks running several Cesium stds don't
be offended I'm not saying your needs are not practical :-)
;-) hi
rently you have both feet there... looking at sub Hz you're infected
that's a fact ;-)
Luis Cupido.
ct1dmk.
Bob Bownes wrote:
First it was building a VE2ZAZ GPSDO with an 10881 I happened across.
Next came the TICII's followed closely by the 5370B. Then the
thunderbolt. Now i
http://spectrum.ieee.org/semiconductors/devices/chipscale-atomic-clock
Luis Cupido
ct1dmk.
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Jim, Bob, Henry, Brian,
Thanks to all.
Very good.
yeap, I do work on matlab so I think there is plenty now
to keep me busy ;-)
tks.
Luis Cupido
ct1dmk.
p.s.(what's cooking)
I need a relatively narrow tunning range
but absolutely free of close in spurs,
willing to see if a modest siz
Hi,
Is there a DDS spur prediction software around ?
I mean for an arbitrary DDS design, like I would
implement with logic or fpga etc.
A code where I can enter nr of bits adc bits etc.
(not a thing for a particular analog-devices chip or
other dds chip)
tks.
Luis Cupido
ct1dmk
the digital part I have no idea, but would not be surprised of
that very simplistic single chip approach sound card chip and an USB
micro to feed the control bits to the PLL chip...
It may well be a very very simple thing hardware wise.
...hence, I'm still curious ;-)
Luis Cupido.
jimlux
Hi Don.
I'm ultra curious of how they did it. How did they covered the
full BW they have.
Did you looked inside, or did they sent a block diagram?
(...I was born curious... it is not a new symptom!)
Luis Cupido.
ct1dmk.
Don Latham wrote:
I have one of the original analyzers, and I
> But they mention software to generate sequences.
Hummm... right...
so I think we need to look inside one to be sure what it is...
lc
ct1dmk.
jimlux wrote:
Luis Cupido wrote:
Hi,
The fact they refer that atmospheric s/n degradation and dropouts etc
being replayed precisely lead me
Hi,
The fact they refer that atmospheric s/n degradation and dropouts etc
being replayed precisely lead me to think this is just a spectrum
rec/play machine (no mod/demod of any kind)
like the ham-oriented "time machine" but for GPS.
http://www.expandedspectrumsystems.com/prod2.
sign...
So many nice stories about gear that worked only with a certain set
of parts way off the manufacturers expressed data...
one day I'll drop a few here just for amusement.
Luis Cupido
ct1dmk.
J. Forster wrote:
FWIW, IMO any engineer who uses undocumented or uncontrolled parameters or
in
en... Look no further ;-) Reflock to 1pps is your thing.
Take a look of all variants by VE1ALQ and G8ACE
(there is also a japanese variation... can't recall).
all those variants may use my reflockI 1pps CPLD config.
Luis Cupido.
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in addition to the
above timings depends on how much you want to average
the 1pps. Having it fast it would obviously
track the 1pps jitter.
'how good you need' -> 'how slow it has to be'
These timings are off course after your GPS starts
producing good enough 1pps pulses.
Tks, Bruce,
Tks, John,
Looks that is it.
(I could not find the info...
must improve my googling skils hi).
Not sure how to decipher the reference but
at least I know it is a 5MHz and know
what kind of performance to expect, in principle.
Many thanks.
Luis Cupido.
ct1dmk.
John Miles wrote
Does anyone has data on the
MTI 230-0546-A OCXO (5MHz).
( If no datasheet, just pinout best guess
may help ).
Many thanks.
Luis Cupido.
ct1dmk.
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the small
wenzels, BLIBEY, OACs and a few more.
Not necessarily just 10MHz... other freqs
are of interest too.
Any generic heading info/help?
Many Thanks.
Luis Cupido.
ct1dmk.
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o longer has them on their web site...
(it was 10 years ago I got it)
More, I'm out of the official DCF77 range and it receives
beautifully (I believe it is due to the fact they used
a big rod ant)
If it helps the find one I can take a picture of mine.
Luis Cupido.
ct1dmk.
Rob Kimberley wrote
e the simple ones gone obsolete, or simple no longer in the
web pages ???
ok... I think you got the idea...
I'm looking for the basic think...
Any suggestions of what might be usable/available.
Thanks.
Luis Cupido
ct1dmk.
p.s. I know it doesn't matter to have a modern comp
Hi Tom,
10log
I have no doubts that money=power...
from years of personal experience of little power ;-)
;-).
Luis Cupido.
ct1dmk.
Tom Holmes, N8ZM wrote:
Hi Luis...
Is that based on 10Log, or 20Log?
I'm thinking Money = Power ;-).
Regards,
Tom Holmes, N8ZM
Tipp City, OH
E
about 16dB down (I think).
:-)
lc
ct1dmk.
Steve Rooke wrote:
Ah! but is it cheaper than US $15,865.00?
On 8 April 2010 01:05, Luis Cupido wrote:
BTW,
I have this recently developed for another application
http://w3ref.cfn.ist.utl.pt/cupido/dl/050.jpg
it has all it takes to make that
from low PN
sources)...
40ke Cyc III fpga has more than enough multipliers and etc
for the sort of conversions and correlations needed...
and the display and fancy interface would happen in the PC.
Anyone feels attracted to do some coding ???
Luis Cupido
ct1dmk
You may try Altera. Quatus web 9.1 is 1.5Gb and painless to setup.
https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp
lc.
ct1dmk.
paul swed wrote:
I also did the web install and need to go back and add more options.
How painful. Enough to drive me away
option to 'see'
how it 'sounds'... and differences 'pop up' to your eyes/years just
like that. ;-)
Luis Cupido.
ct1dmk
P.S. I did a lot of exprimentation long time ago when I was palying with
the LO for the DSN rx, where I was looking for phase noise to be quite
low at
eral terms anymore.
Luis Cupido.
ct1dmk.
Gerhard Hoffmann wrote:
Luis Cupido wrote:
That is not by any means a CPLD. it is a big FPGA and I bet it would
be doing a bazilon things besides the divider.
It shares the CPLD's problems of ground and VCC bounce. The Virtex
was completely empty ot
(designed
properly) and "Nothing Else" inside.
Luis Cupido
ct1dmk.
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Gerhard,
That is not by any means a CPLD. it is a big FPGA and I bet it would
be doing a bazilon things besides the divider.
Hummm... not really adds to the original question I'm afraid ;-)
Luis Cupido,
ct1dmk.
Gerhard Hoffmann wrote:
I have done that with a Virtex4-SX on a ML402 boar
setup you might think of).
Way better than TTL.
Luis Cupido.
ct1dmk.
Matt Ettus wrote:
Does anyone have any experience using CPLDs for very low phase noise
dividers? You can get an XC9536XL from Xilinx for around $1, and I
thought it would make a good divide by 2 through 10 device.
Matt
Frank,
You might want to take a look in here also.
Hardly gets any simpler than this ;-)
http://w3ref.cfn.ist.utl.pt/cupido/reflock.html
Luis Cupido
ct1dmk.
On 02/02/10 16:50, francesco messineo wrote:
Hello all,
sorry for the OT, but I know there're many real electronic artists here
But only starts at 5GHz :-( :-(
Luis Cupido
ct1dmk
John Miles wrote:
You could also get really hardcore and build the VNA described in DUBUS
4/2009 by HB9TXV. Very nice piece of work, usable to 30 GHz.
-- john, KE5FX
-Original Message-
From: time-nuts-boun...@febo.com
Hi Glen,
Looks indeed like an SMP but I believe it
is a siemens 1.0/2.3 used on the DIN41612
backplanes (note the retention spring in the back
to allow them to lock inside the 41612/M connectors
shell).
Luis Cupido.
ct1dmk.
p.s. don't know if 1.0/2.3 connectors will
mate with SMP o
Hi Robert,
... 43 or BT43 (BT=British Telecom) is a private
reference only for British. hi ;-)
It is 1.6/5.6 for the rest of us.
(patent is siemens afaik)
Luis Cupido.
ct1dmk.
Robert Atkinson wrote:
Hi Peter,
They are Type 43 or BT43 connectors. 75R used in telecomms digital equipment in
e, and I could have activity (both
building/setting-up and operating) orders of magnitude higher than I
could possibly handle.
My 2cents to help changing the general misconception that above HF there
is very little do do... On the contrary...
> many of us don't even have HF antenna
Brian,
Wow, a lot of nice reading I have here.
Thanks.
Luis Cupido.
ct1dmk.
brimda...@aol.com wrote:
Luis wrote:
I'm looking for the schemes used on the frequency synthesizers
that change frequency in few microseconds time (or less)
Does anyone know of some paper or tech notes
My fear is "in the loop bandwidth" is a lot of BW
as I need a wide loop for it to be fast.
Okay, it sounds a nice path to investigate.
tks.
lc
Lux, Jim (337C) wrote:
On 10/15/09 5:56 AM, "Luis Cupido" wrote:
Hi Bert,
Thanks for the input.
briefly;
-Phase noise is n
prototype of that.
The second one I must check how small would be the step...
1 MHz would be enough for a start.
Thanks
Luis Cupido.
ewkeh...@aol.com wrote:
Luis
There is not really enough information to make a good recommendation. Is
this a one off or is the plan to make multiple units, what
tabled point to get the right DAC value.
(uC times are not to be considered here as all calculations
are done much before during the so called setup time)
So cleverness on board (i.e. microprocessor and
soft) is not a problem for the application.
My issue is RF and microwave simplicity ;-)
tk
te myself if I start this design while missing a
much simpler approach.
That is the nearly the full story.
A lot more comments can come
and I will be happy an thankful.
Thanks.
Luis Cupido.
ct1dmk.
Hi John.
John Miles wrote:
Pretuning is the right strategy, but for microsecond agility, YIGs may
hing times (millisencods or more).
Info on fast stuff I can't really find.
I'm thinking of experimenting on something along those
lines so... all comments are welcome.
Thanks.
Luis Cupido.
ct1dmk.
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Hi,
Depending how deep you want, to go you must
note that this one from ve2zaz (btw which is a great
design given it's simplicity) is a FLL not a PLL.
(unlike most of the others that really lock the phase of the
signal to the 10KHz or 1pps).
Luis Cupido.
ct1dmk.
Roberto Barrios
Hi Dick,
'cause it may not integrate long enough...
'cause it may have poor phase noise...
;-)
(it is however a very good question though, as one must
be really sure what it does and then be motivated to improve it...)
Luis Cupido
ct1dmk.
Richard W. Solomon wrote:
Dumb question
Nic,
I think yes but I'm not sure, please check
Darrel's VE1ALQ and NTMS(Kent Britain) for
reflock I pcb's and/or kits (as I've not heard
from them recently).
I believe TAPR is no longer offering the
reflock II kit :-(
Luis Cupido
ct1dmk.
Nic McLean wrote:
Hi Luis,
Are
10MHz you can use the same
reflock I design and the configuration is kind of trivial
(but no one asked for it before) and I can make a file
for you.
Luis Cupido
ct1dmk.
From: Bruce Griffiths
To: Discussion of precise time and frequency measurement
Sent
Hi,
I do have a HP5335A and after the many comments
about the 5370 I'm curious if there is something
I'd be better off with the 5370 instead of my 5334
I've read the specs of both but... better ask
the experts ;-)
Luis Cupido.
ct1dmk.
__
I believe it is to be ham or hobby oriented
Am I right ?
(If so some rewording of the list purpose
might be adequate... thinking out loud...)
Luis Cupido
ct1dmk.
Scott Newell wrote:
> At 12:29 PM 4/14/2009 , John Miles wrote:
>> ... for those who would like to participate in HDL discuss
he same 74HC244 (adding a few bits to the
original byteblasterMV for the additional features required)
and it works just fine even with Cyclone devices.
Luis Cupido.
ct1dmk.
Bruce Griffiths wrote:
> Luis Cupido wrote:
>>
>>> The CPLDs are programmed via the JTAG port.
>>
> The CPLDs are programmed via the JTAG port.
> Suitable JTAG programming cables are readily availble.
Or you can build one to use the LPT port of your PC using just a 74HC244.
Luis Cupido.
ct1dmk.
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Brian,
Was there any particular reason to
go from 5MHz to 20MHz in two steps ?
couldn't be just one x4 stage followed by the filter
(preferably xtal) ?
Luis Cupido.
ct1dmk.
wa1...@att.net wrote:
> John-
>
> The BPFs in the 5 to 20MHz chain are just 7-pole LC
> filters with t
version is against you so
not sure if better or worst.
Luis Cupido
ct1dmk.
(*) x12 x9 x3 x2
w/ 9th harm corner cube harm mixer
if my memory serves me well
wa1...@att.net wrote:
> Bruce-
>
> OK... So, linear operation does therefore seem to be the preferred
> way to operate t
Bruce,
John,
Tks for all your comments about that topic.
really interesting.
Luis Cupido.
ct1dmk.
Bruce Griffiths wrote:
> Luis Cupido wrote:
>> Bruce,
>> John,
>> ...
>>
>> And at smaller offsets like 100Hz and less ?
>> Shouldn't the improvement
LO's and etc.
Am I right ?
Luis Cupido.
ct1dmk.
Bruce Griffiths wrote:
> Luis
>
> The R+S FMU36 has a phase noise floor of around -143dBc/Hz (offset >
> 10kHz) with a 10MHz input.
> Whereas the R+S FSU67 has a phase noise floor of around -133dBcdBc/Hz
> (offs
ultiplied by 10 maximum.
How can they claim similar performance ?!
---
Ok on the rest, tks.
Luis Cupido.
Bruce Griffiths wrote:
> Luis
>
> The latest spectrum analyser offerings from Agilent have similar phase
> noise floors for both the millimeter wave and low frequency
anyway, Or then I have to live with what my
spectrum analyzer show me (a tek 492, in my case).
---
Rephrasing the question, how much better are the low frequency
spectrum analyzers comparing to the microwave spectrum
analysers (in phase noise I mean)?
Any comments ?
Luis Cupido.
ct1dmk.
P.S.(I
here are better ones...
my 2 cents ;-)
Luis Cupido.
ct1dmk.
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>There are any number of
>choices, including the PIC line, which everyone but me seems to love.
Bill,
You're not alone ;-)
Luis Cupido.
ct1dmk.
wje wrote:
>My favorite for many uses is the Freescale MC68HC908QT4, or others in
>that series. Freescale provides a compl
All the rest is crap compared to this...
At least in my experiments.
discrete but simple...
sometimes super-duper ic's are not the best option.
Luis Cupido.
ct1dmk.
p.s. my interest was wide band so filtering amplifying and clipping
(by far the best solution) was not an option for me.
We dont get much info/comments about this
But what would an ammonia cell standard be able to do.
I mean frequency/time wise.
Maybe easier and simpler ?
comments ?
Luis Cupido.
ct1dmk.
(I understand the frequencies are much higher
but that is not a problem, at least for me
using only a tiny fraction of the information available.
...
interesting topic :-)
Luis Cupido.
p.s.
however even tens of thousands of measurements
of 1ms windows is a few minutes !!!
Bruce Griffiths wrote:
> Probably impractical as the sampling noise is so high that it will
&g
Right...
Not necessarily an FFT, other transforms are
quite well suited to this.
FFT was just my quick way to let the idea out ;-).
lc.
Magnus Danielson wrote:
> From: Luis Cupido <[EMAIL PROTECTED]>
> Subject: Re: [time-nuts] Fast frequency counting question
> Date: Mon, 05 Ma
Couldn't it be:
digitizing, process the data with a sliding FFT
(making a spectrogram) plus deconvolve
with the system line broadening response,
and if all chirps are equal then repeating
the above N times for resolution increase.
Luis Cupido
ct1dmk.
Pete wrote:
> Murray,
>
> I
Tested, It works great.
tks.
lc
ct1dmk.
[EMAIL PROTECTED] wrote:
> Was it VisualGPS??
>
> www.visualgps.net
>
> 73,
> Mike, N1JEZ
> "A closed mouth gathers no feet"
>
> ----- Original Message -
> From: "Luis Cupido" <[EMAIL PROTEC
Tks, Mike,
It was something very similar
Will try that one tks.
Luis Cupido.
ct1dmk.
[EMAIL PROTECTED] wrote:
> Was it VisualGPS??
>
> www.visualgps.net
>
> 73,
> Mike, N1JEZ
> "A closed mouth gathers no feet"
>
> ----- Original Message -
> From
Hi Tom,
That I know ;-)
I meant something more visual :-)
Tks anyway.
Luis Cupido.
ct1dmk.
Tom Clifton wrote:
> From: Luis Cupido <[EMAIL PROTECTED]>
> Can anyone point me to any simple program, must run
> on older machines (windows 98) be and free.
> I mean very basi
point me to any simple program, must run
on older machines (windows 98) be and free.
I mean very basic stuff for sanity checks of system
antena etc.
Thanks.
Luis Cupido.
ct1dmk.
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Tks Dean,
Not yet ruled out a silly mistake (so thanks for
the tips, double check it again)... but...
as you saw on my previous post it looks
like this is a peculiarity of this PC the
south bridge or whatever as on others it seems to work
fine.
tks, for the book reference ;-) will look for it.
lc
board.
:-(
So it is not reading from isa !!!
I'm interfacing an FPGA to it and got stuck
with this issue.
It works with a good old 486 though ;-)
Thanks for help.
Luis Cupido.
ct1dmk.
Stanley Reynolds wrote:
>
> - Original Message ----
> From: Luis Cupido <[EMAIL PROTE
lines forced '0' all the time)
Looks that IO input is comming from elsewhere
as onboard devices like LPT or COM work well
I suspect a bridge config or whatever...
Kontron support doesn't really help and I
wonder if anyone has stepped into this before...
Thanks and sorry for off topic.
l PIC
(is it a challenge or idiocy ???)
- Someone blinking a led with a ARM
or a black-fin etc.
(just avoiding to learn 2 pic instructions !!!)
- Someone doing a tricky job using a
micro-controller to do something that
is a simple logic job, CPLD or whatever.
Luis Cupido.
ct1dmk
P.S.Wishing to be pro
not
any real performance tests on it only some
basic functional tests :-(
... I'm stuck to 1pps ;-)
Luis Cupido.
ct1dmk
http://w3ref.cfn.ist.utl.pt/cupido/
Dave Brown wrote:
> There's a published design very similar to James Millers from Andy
> Talbot-
>
> http://ww
Ok. I understand now what you suggest.
Thanks for the explanation.
Luis Cupido.
ct1dmk.
Bruce Griffiths wrote:
> Luis Cupido wrote:
>> Bruce,
>>
>> > No analog filtering of the D flipflop output is required.
>>
>> Now you got me lost.
>>
>>
that is similar, better or still
worst than HC or AC.
Yeap... Nice thing to test
Hummm... I'm still thinking how to test such... :-)
Luis Cupido.
ct1dmk.
michael taylor wrote:
> On Dec 12, 2007 7:33 AM, Luis Cupido <[EMAIL PROTECTED]> wrote:
>> Very good, I do respect the
e)
So by the end of it you need an analog
signal to control the voltage input of the VCXO. Right ?
Where you get that from ?
If not by filtering your flip-flop output
what else you have in between the 1pps and the VCXO ?
CPU's DAC's
if so how does your comp
t it simple as you say
I presume you have also to filter in analog ?!
So you end up with a slightly worst phase comparator
and the less convenient analog filter :-(
Or do you need to add a microcontroller and a DAC ?
If that is the case, there goes off your complexity issue
much
croporcessors + dac (in which some noise did get through),
or lack stability.
Luis Cupido
ct1dmk.
http://w3ref.cfn.ist.utl.pt/cupido/
Bruce Griffiths wrote:
> Scott
>
> Scott Burris wrote:
>> OK, so for the DAC piece, why not just use an NXP LPC ARM chip for the
>> mi
Scott, you have also:
http://w3ref.cfn.ist.utl.pt/cupido/reflock.html
lab grade consider using reflock II
for kits I think TAPR still has those...
Luis Cupido
ct1dmk.
Scott Burris wrote:
> Hi,
>
> Like many, I've acquired a fair amount of surplus test equipment off of Ebay
>
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