Message-
> From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On
> Behalf Of Bob Camp
> Sent: August-30-13 1:21 PM
> To: Discussion of precise time and frequency measurement
> Subject: Re: [time-nuts] frequency multiplication
>
> Hi
>
>
time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf
Of Bob Camp
Sent: August-30-13 1:21 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] frequency multiplication
Hi
A discrete VCXO and PLL chip will always outperform the "buit in VCO&
Hi
A discrete VCXO and PLL chip will always outperform the "buit in VCO" silicon
parts. The CY2302 is quite noisy even by silicon standards. Your doubler /
tripler will give you good close in noise, but poor performance broadband. A
lot depends on what the ultimate use for the DDS output is. Th
Good day all,
Lately I have been contemplating a variety of methods to take a high stability
10 MHz reference multiply it up to a suitable frequency for use a the reference
clock for a DDS, for example 10 MHz to 80 MHz or 120 MHz (or whatever).
On method is to use simple diode based doublers
> > Hopefully you mean this along the lines of: should you decide to feed two
> > different clocks into the Virtex-2, and use the dedicated global clocks,
then
> > you guess the isolation between those 2 global clock lines to be on the
order
> > of about 20-30 dB. So basically...
> No guessing..
On 2/5/11 10:20 PM, Tijd Dingen wrote:
You don't feed the ADC from the FPGA if you can avoid it.
especially if your ADC clock is a different frequency from the processor
clock that's being used for most of the other logic on the FPGA. I'd
give a ballpark estimate of 20-30 dB isolation between
> > You don't feed the ADC from the FPGA if you can avoid it.
> especially if your ADC clock is a different frequency from the processor
> clock that's being used for most of the other logic on the FPGA. I'd
> give a ballpark estimate of 20-30 dB isolation between the two on a
> Virtex 2.
I r
On 05/02/11 15:20, jimlux wrote:
I agree, but if you want the clock rate to be changeable/selectable,
driven arbitrarily by logic in the FPGA, you're kind of stuck.
There is always corner-cases. I quite intently left room for that as
well. The general recommendation is still to avoid it unless
On 2/5/11 3:54 AM, Magnus Danielson wrote:
On 05/02/11 12:13, jimlux wrote:
And where in-situ changes in the signal processing are needed (e.g. in a
software defined radio), the reprogrammable FPGA is a good fit. But
there is a tradeoff.. you might want to give the downstream
users/programmers t
On 05/02/11 12:13, jimlux wrote:
And where in-situ changes in the signal processing are needed (e.g. in a
software defined radio), the reprogrammable FPGA is a good fit. But
there is a tradeoff.. you might want to give the downstream
users/programmers the ability to change sample rates, prompting
On 2/5/11 3:04 AM, Magnus Danielson wrote:
On 05/02/11 04:33, jimlux wrote:
On 2/4/11 1:18 PM, Magnus Danielson wrote:
On 02/02/11 19:47, Hal Murray wrote:
Bottom line - there's a lot to look into, and they are unlikely to
help you
out.
There are a lot of FPGAs used in DSP applications whe
On 05/02/11 04:33, jimlux wrote:
On 2/4/11 1:18 PM, Magnus Danielson wrote:
On 02/02/11 19:47, Hal Murray wrote:
Bottom line - there's a lot to look into, and they are unlikely to
help you
out.
There are a lot of FPGAs used in DSP applications where the clock to the
front end ADC is critica
On 2/4/11 1:18 PM, Magnus Danielson wrote:
On 02/02/11 19:47, Hal Murray wrote:
Bottom line - there's a lot to look into, and they are unlikely to
help you
out.
There are a lot of FPGAs used in DSP applications where the clock to the
front end ADC is critical. So I'd expect there would be so
On 04/02/11 22:50, Rex wrote:
On 2/4/2011 1:18 PM, Magnus Danielson wrote:
Just avoid falling into the charge-pump tar-pit...
Cheers,
Magnus
Curious what you mean by that?
If you have the combination of a charge-pump with a dead-band (such as
4046) and a too low comparator frequency... yo
On 2/4/2011 1:18 PM, Magnus Danielson wrote:
Just avoid falling into the charge-pump tar-pit...
Cheers,
Magnus
Curious what you mean by that?
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On 02/02/11 19:47, Hal Murray wrote:
Bottom line - there's a lot to look into, and they are unlikely to help you
out.
There are a lot of FPGAs used in DSP applications where the clock to the
front end ADC is critical. So I'd expect there would be some in-house
knowledge about this area. It
the same logic, all of the office space in New York could not fit
> in New York. But it does because they stack it 20 or 100 floors one
> on top of the other.
>
> I suspect the areas will overlap with very dense coverage in urban
> areas. Perhaps in some places there is 50
FPGA's do not have good jitter performance. Both Altera and Xilinx have
app notes and specs on what to expect for jitter performance.
Particularly when using high speed DACs (like the ADI AD9739) the
technique used is to drive the DAC with a good quality clock, then the
DAC drives the FPGA.
> Bottom line - there's a lot to look into, and they are unlikely to help you
> out.
There are a lot of FPGAs used in DSP applications where the clock to the
front end ADC is critical. So I'd expect there would be some in-house
knowledge about this area. It may be that all the help you will
unlikely to help you
out.
Bob
-Original Message-
From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On
Behalf Of Geraldo Lino de Campos
Sent: Wednesday, February 02, 2011 12:23 PM
To: time-nuts@febo.com
Subject: [time-nuts] Frequency multiplication
Followin
Following the thread on frequency multiplication, does someone know about
the phase noise of the FPGAs PLLs? I couldn't find information on this.
If phase noise is acceptable, it can be a flexible and economical solution.
--
Geraldo
gera...@decampos.net
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