will be:
Saving Environment to SPIFlash... Failed (-12)
Note that there is another copy of env_sf_save() in the same file, for
handling redundant environment, and it already has the same logic.
Signed-off-by: Ralph Siemsen
---
env/sf.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
to u-boot v2023.04-rc2
- reviewer suggestions added to spkgimage.c
- many small cleanups, checkpatch, FIXMEs resolved
Changes in v2:
- rewrote the stand-alone spkg_utility to integrate into mkimage
Ralph Siemsen (10):
ARM: armv7: add non-SPL enable for Cortex SMPEN
clk: renesas: prepare for
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
(no changes since v6)
Changes in v6
-snarc/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
Reviewed-by: Simon Glass
Reviewed-by: Marek Vasut
As a starting point, list all currently supported Renesas boards.
For the RZ/N1 board, add details about booting and flashing.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
Changes in v7:
- replace broken link to binman.rst
Changes in v5:
- added renesas dir to doc/board
for this family, modeled on the existing RZA1.
Signed-off-by: Ralph Siemsen
---
(no changes since v6)
Changes in v6:
- make the #ifdef a bit clearer
Changes in v5:
- fold mach-rzn1 into mach-rmobile
arch/arm/mach-rmobile/Kconfig | 19 +++
arch/arm/mach-rmobile/Kconfig.rzn1 | 20
This is taken directly from Linux kernel 6.3
(commit 457391b0380335d5e9a5babdec90ac53928b23b4)
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
(no changes since v6)
Changes in v6:
- updated comment to reflact linux 6.3, and add commit hash.
(the files themselves have not changed
temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
(no changes since v6)
Changes in v6:
- add macros for RSTEN register and its bits
Changes in v5:
- eliminate "err" in probe function
Changes in v4:
- commit message now includes hash
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen
---
(no changes since v6)
Changes in v6:
- use wait_for_bit macros instead of endless while loop
Changes in v5:
- move board-specific init out of the driver.
Changes in v3:
- assorted small
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
(no changes since v5)
Changes in v5:
- add R-b tag
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off
support code. The support code contains platform specific
access (TMU_BASE) which is not needed on other Renesas devices such as
RZ/N1.
Signed-off-by: Ralph Siemsen
Reviewed-by: Sean Anderson
Reviewed-by: Marek Vasut
---
(no changes since v5)
Changes in v5:
- add symbol CONFIG_CLK_RCAR and select
:
- rewrote the stand-alone spkg_utility to integrate into mkimage
Ralph Siemsen (10):
ARM: armv7: add non-SPL enable for Cortex SMPEN
clk: renesas: prepare for non R-Car clock drivers
clk: renesas: add R906G032 driver
pinctrl: renesas: add R906G032 driver
ram: cadence: add driver for Cadence
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
Changes in v6:
- move board-specific DDR
As a starting point, list all currently supported Renesas boards.
For the RZ/N1 board, add details about booting and flashing.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
(no changes since v5)
Changes in v5:
- added renesas dir to doc/board/index.rst
- corrections to list
-snarc/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
Reviewed-by: Simon Glass
Reviewed-by: Marek Vasut
temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
Changes in v6:
- add macros for RSTEN register and its bits
Changes in v5:
- eliminate "err" in probe function
Changes in v4:
- commit message now includes hash of Linux upon which thi
for this family, modeled on the existing RZA1.
Signed-off-by: Ralph Siemsen
---
Changes in v6:
- make the #ifdef a bit clearer
Changes in v5:
- fold mach-rzn1 into mach-rmobile
arch/arm/mach-rmobile/Kconfig | 19 +++
arch/arm/mach-rmobile/Kconfig.rzn1 | 20
arch
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen
---
Changes in v6:
- use wait_for_bit macros instead of endless while loop
Changes in v5:
- move board-specific init out of the driver.
Changes in v3:
- assorted small cleanups
- support
This is taken directly from Linux kernel 6.3
(commit 457391b0380335d5e9a5babdec90ac53928b23b4)
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
Changes in v6:
- updated comment to reflact linux 6.3, and add commit hash.
(the files themselves have not changed)
Changes in v5
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
(no changes since v5)
Changes in v5:
- add R-b tag
support code. The support code contains platform specific
access (TMU_BASE) which is not needed on other Renesas devices such as
RZ/N1.
Signed-off-by: Ralph Siemsen
Reviewed-by: Sean Anderson
Reviewed-by: Marek Vasut
---
(no changes since v5)
Changes in v5:
- add symbol CONFIG_CLK_RCAR and select
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off
On Tue, May 09, 2023 at 11:42:30AM -0400, Ralph Siemsen wrote:
On Tue, May 09, 2023 at 04:52:45PM +0200, Marek Vasut wrote:
Do we have some sort of global (?) state structure which exists
during the whole work cycle of the tool ? If so, add a link list
into there.
There is struct
On Tue, May 09, 2023 at 09:21:02AM -0400, Ralph Siemsen wrote:
On Tue, May 09, 2023 at 04:26:57AM +0200, Marek Vasut wrote:
On 5/8/23 20:23, Ralph Siemsen wrote:
I moved it to board-specific directory as an interim step.
Hopefully we can do some consolidation of the multiple CDNS DDR
On Tue, May 09, 2023 at 04:52:45PM +0200, Marek Vasut wrote:
Do we have some sort of global (?) state structure which exists during
the whole work cycle of the tool ? If so, add a link list into there.
There is struct image_tool_params which is passed to the callbacks and
holds most of the
On Tue, May 09, 2023 at 04:26:57AM +0200, Marek Vasut wrote:
On 5/8/23 20:23, Ralph Siemsen wrote:
I moved it to board-specific directory as an interim step. Hopefully
we can do some consolidation of the multiple CDNS DDR controller
implementations, and then figure out the right way to split
On Tue, May 09, 2023 at 04:25:06AM +0200, Marek Vasut wrote:
The usual fail path handling like:
"
if (there is an error)
goto exit;
...
exit:
free(data);
return ret;
"
does not work here ?
Yes, this would handle de-allocation in the failing case.
However in the normal case (no error),
On Sun, May 07, 2023 at 06:06:40PM +0200, Marek Vasut wrote:
On 4/24/23 03:15, Ralph Siemsen wrote:
Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle
On Sun, May 07, 2023 at 06:08:33PM +0200, Marek Vasut wrote:
[...]
+static int spkgimage_parse_config_file(char *filename)
+{
+ FILE *fcfg;
+ char line[256];
+ size_t line_num = 0;
+
+ fcfg = fopen(filename, "r");
+ if (!fcfg)
+ return -EINVAL;
+
+
Ralph Siemsen (10):
ARM: armv7: add non-SPL enable for Cortex SMPEN
clk: renesas: prepare for non R-Car clock drivers
clk: renesas: add R906G032 driver
pinctrl: renesas: add R906G032 driver
ram: cadence: add driver for Cadence EDAC
ARM: dts: add devicetree for Renesas RZ/N1 SoC
ARM
Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
Changes in v5:
- put all local DTS
-snarc/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
Reviewed-by: Simon Glass
squash! tools: spkgimage
As a starting point, list all currently supported Renesas boards.
For the RZ/N1 board, add details about booting and flashing.
Signed-off-by: Ralph Siemsen
---
Changes in v5:
- added renesas dir to doc/board/index.rst
- corrections to list of Renesas boards
- move RZ/N1 detail into its own
This is taken directly from Linux kernel 6.3-rc7.
Signed-off-by: Ralph Siemsen
---
Changes in v5:
- r9a06g032.dtsi now identical to linux 6.3-rc7 version
Changes in v3:
- add syscon phandle to ddrctl
- simplify UART compatible strings
arch/arm/dts/r9a06g032.dtsi | 477
temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
---
Changes in v5:
- eliminate "err" in probe function
Changes in v4:
- commit message now includes hash of Linux upon which this is based
as well as the additional patches (clock table cleanups)
- sync changes from rev
for this family, modeled on the existing RZA1.
Signed-off-by: Ralph Siemsen
---
Changes in v5:
- fold mach-rzn1 into mach-rmobile
arch/arm/mach-rmobile/Kconfig | 19 +++
arch/arm/mach-rmobile/Kconfig.rzn1 | 20
arch/arm/mach-rmobile/cpu_info.c | 8
3
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
Changes in v5:
- add R-b tag
drivers/pinctrl
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen
---
Changes in v5:
- move board-specific init out of the driver.
Changes in v3:
- assorted small cleanups
- support version 1.0 silicon (previously #if 0...)
drivers/ram/Kconfig
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off
support code. The support code contains platform specific
access (TMU_BASE) which is not needed on other Renesas devices such as
RZ/N1.
Signed-off-by: Ralph Siemsen
Reviewed-by: Sean Anderson
---
Changes in v5:
- add symbol CONFIG_CLK_RCAR and select it for R-Car Gen2/3.
- use this to control
On Tue, Apr 18, 2023 at 3:36 PM Marek Vasut wrote:
> I'm afraid this needs some backward compatibility sreccat version check
> . Similar to GCC compiler flags presence check. To avoid breaking legacy
> users.
I'll revisit this after the rz/n1 work, which is more important.
Also I noticed that
The -l-e-constant flag has been deprecated since 2012. [1]
Use the recommended replacement instead.
[1] https://sourceforge.net/p/srecord/code/ci/1.59.D009/
Signed-off-by: Ralph Siemsen
---
arch/arm/mach-rmobile/Makefile | 48 +-
1 file changed, 24 insertions
On Mon, Apr 17, 2023 at 4:21 PM Marek Vasut wrote:
>
> On 4/17/23 20:26, Ralph Siemsen wrote:
> > On Mon, Apr 17, 2023 at 07:04:15PM +0200, Marek Vasut wrote:
> >> You could send this patch as a separate one.
> >
> > In fact I did that almost a year ago:
&
On Mon, Apr 17, 2023 at 10:34:08PM +0200, Marek Vasut wrote:
On 4/17/23 22:29, Ralph Siemsen wrote:
Indeed it does, see below. I did however want to document how to call
mkimage manually, since it took me a while to work out the right
arguments (especially using -n for the config file
On Mon, Apr 17, 2023 at 10:33:18PM +0200, Marek Vasut wrote:
On 4/17/23 20:22, Ralph Siemsen wrote:
Perhaps we could change Kconfig to select CPG also for gen2. I can
make this patch, but how to test that this does not introduce any new
problems? Might there be an autobuilder for R-Car
On Mon, Apr 17, 2023 at 10:30:26PM +0200, Marek Vasut wrote:
I mean, if you drop 'CLK' and 'CLK_RENESAS' from this list, do they
still get selected because 'CLK_R8A06G032' is in this list ? If yes,
then drop them from this list, else keep them.
If I drop the first two, I get some kconfig
On Mon, Apr 17, 2023 at 07:32:30PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
[...]
+#define FUNCCTRL 0x00
+#define FUNCCTRL_MASKSDLOFS (0x18 << 16)
+#define FUNCCTRL_DVDDQ_1_5V (1 << 8)
+#define FUNCCTRL_RESET_N (1 << 0
On Mon, Apr 17, 2023 at 07:28:05PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
RZ/N1
+- Schneider rzn1-snarc board
+
+Building
+
+
+NOTE: the following information is for the rzn1 board only.
Maybe this should be in a separate document , some rzn1 specific
On Mon, Apr 17, 2023 at 07:23:46PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
+ spkgimage.o \
Maybe just call the file renesas_spkgimage.o so its clear which
SoC/vendor this file is associtated with.
Okay, will do.
+static struct spkg_file
On Mon, Apr 17, 2023 at 07:18:46PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
diff --git a/board/schneider/rzn1-snarc/ddr_timing.c
b/board/schneider/rzn1-snarc/ddr_timing.c
new file mode 100644
index 00..8bc3fe7be4
--- /dev/null
+++ b/board/schneider/rzn1-snarc
On Mon, Apr 17, 2023 at 07:15:07PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
[...]
+++ b/arch/arm/Kconfig
@@ -1031,6 +1031,21 @@ config ARCH_RMOBILE
imply SYS_THUMB_BUILD
imply ARCH_MISC_INIT if DISPLAY_CPUINFO
+config ARCH_RZN1
+ bool "Renea
On Mon, Apr 17, 2023 at 07:12:31PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
This is taken from Linux kernel 5.17, and contains just bare minimum
functionality: CPU, UART and system timer.
Why Linux 5.17 and not e.g. 6.2 or 6.1 LTS ?
It was the current version
On Mon, Apr 17, 2023 at 07:07:57PM +0200, Marek Vasut wrote:
R-Car , not RCAR .
Ack, will fix in next version (including in some commit msg)
+static int r9a06g032_clk_probe(struct udevice *dev)
+{
+ struct r9a06g032_priv *priv = dev_get_priv(dev);
+ int err;
+
+
On Mon, Apr 17, 2023 at 07:04:15PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the correspondi
Hi Marek,
On Mon, Apr 17, 2023 at 07:02:34PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
diff --git a/drivers/clk/renesas/Makefile
b/drivers/clk/renesas/Makefile
index 8f82a7aa3e..a0d8c10bdb 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
resolved
Changes in v2:
- rewrote the stand-alone spkg_utility to integrate into mkimage
Ralph Siemsen (10):
ARM: armv7: add non-SPL enable for Cortex SMPEN
clk: renesas: prepare for non-RCAR clock drivers
clk: renesas: add R906G032 driver
pinctrl: renesas: add R906G032 driver
ram: cadence: add
Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
Changes in v4:
- add binman support
Collect the list of currerently supported Renesas boards.
For the RZ/N1 board, add details about booting and flashing.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
doc/board/renesas/index.rst | 9 +++
doc/board/renesas/renesas.rst | 115 ++
2
of ARCH_RZN1 symbol.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
arch/arm/Kconfig | 17 +
arch/arm/Makefile | 1 +
arch/arm/mach-rzn1/Kconfig| 18 ++
arch/arm/mach-rzn1/Makefile | 3 +++
arch/arm/mach-rzn1/cpu_info.c
-snarc/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
Reviewed-by: Simon Glass
---
Changes in v4
structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
---
Changes in v4:
- commit message now includes hash of Linux upon which this is based
as well as the additional patches (clock table cleanups)
- sync changes from review on linux patches, including
- move RB macro higher up an
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen
---
(no changes since v3)
Changes in v3:
- assorted small cleanups
- support version 1.0 silicon (previously #if 0...)
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile
This is taken from Linux kernel 5.17, and contains just bare minimum
functionality: CPU, UART and system timer.
Additional functionality (from newer kernel versions) will be added
later. Note that the Linux side is under active development.
Signed-off-by: Ralph Siemsen
---
The following changes
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
drivers/pinctrl/Makefile | 1
.
The support code contains platform specific hardware access (TMU_BASE),
and it is not needed for other Renesas devices such as RZ/N1. Therefore,
alter Makefile to build renesas-cpg-mssr.c only for RCAR-GEN2/3.
Signed-off-by: Ralph Siemsen
Reviewed-by: Sean Anderson
---
(no changes since v3)
Changes
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off
On Fri, Feb 24, 2023 at 10:19:53AM -0500, Ralph Siemsen wrote:
Hi Bryan,
On Thu, Feb 23, 2023 at 2:54 PM Bryan Brattlof wrote:
Hi Ralph!
Love seeing more boards here, though I know of a few chips that use some
type of cadence controller. I'm just curious if it would it make sense
to name
Hi Marek,
On Fri, Feb 24, 2023 at 12:05 PM Marek Vasut wrote:
>
> Could you at least submit the clean up to Linux and then sync the result
> to U-Boot, and indicate the Linux clock table came from commit
> with extra patch on top ?
Yes will do. I am refreshing my linux-side patch as we speak.
Hi Bryan,
On Thu, Feb 23, 2023 at 2:54 PM Bryan Brattlof wrote:
>
> Hi Ralph!
> Love seeing more boards here, though I know of a few chips that use some
> type of cadence controller. I'm just curious if it would it make sense
> to name this with some type of Renesas specific branding?
Indeed
On Thu, Feb 23, 2023 at 9:09 AM Miquel Raynal wrote:
>
> Hi Marek,
>
> marek.va...@mailbox.org wrote on Thu, 23 Feb 2023 14:56:41 +0100:
> >
> > Either way is fine by me, I just want to be sure the u-boot clock tables
> > are in sync with Linux as much as possible, and can be easily resynced in
Hi Simon,
Thanks for your review!
On Wed, Feb 22, 2023 at 2:17 PM Simon Glass wrote:
>
> Can you please add some details to doc/ for this SoC and how it boots,
> the use of mkimage, etc.?
Sure, I will cobble something together. Any particular good examples
to look at for inspiration?
> Also
This should fix a rendering oddity when viewing the docs online at
https://u-boot.readthedocs.io/en/latest/develop/package/binman.html
Signed-off-by: Ralph Siemsen
---
tools/binman/binman.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/binman/binman.rst b/tools
On Wed, Feb 22, 2023 at 07:45:45PM +0100, Marek Vasut wrote:
On 2/22/23 19:32, Ralph Siemsen wrote:
On Wed, Feb 22, 2023 at 06:47:44PM +0100, Marek Vasut wrote:
Are those fixes in mainline Linux ?
Yes, they are in mainline:
2dee50ab9e72 clk: renesas: r9a06g032: Fix UART clkgrp bitsel
On Wed, Feb 22, 2023 at 06:47:44PM +0100, Marek Vasut wrote:
On 2/22/23 18:21, Ralph Siemsen wrote:
On Wed, Feb 22, 2023 at 06:07:45PM +0100, Marek Vasut wrote:
On 2/22/23 17:57, Ralph Siemsen wrote:
On Wed, Feb 22, 2023 at 05:06:14PM +0100, Marek Vasut wrote:
On 2/22/23 16:44, Ralph Siemsen
Hi Sean,
I finally got around to posting v3 of this patch series. I wanted to
touch on a few issues you had mentioned in previous review.
On Fri, Aug 26, 2022 at 11:47 AM Ralph Siemsen wrote:
>
> On Tue, Aug 23, 2022 at 12:14:31AM -0400, Sean Anderson wrote:
> >>Regarding th
On Wed, Feb 22, 2023 at 06:07:45PM +0100, Marek Vasut wrote:
On 2/22/23 17:57, Ralph Siemsen wrote:
On Wed, Feb 22, 2023 at 05:06:14PM +0100, Marek Vasut wrote:
On 2/22/23 16:44, Ralph Siemsen wrote:
Clock driver for the Renesas RZ/N1 SoC family. This is based
on the Linux kernel drivers/clk
On Wed, Feb 22, 2023 at 05:06:14PM +0100, Marek Vasut wrote:
On 2/22/23 16:44, Ralph Siemsen wrote:
Clock driver for the Renesas RZ/N1 SoC family. This is based
on the Linux kernel drivers/clk/renesas/r9a06g032-clocks.c.
For starters, can you please include the exact kernel version ,
ideally
v2023.04-rc2
- reviewer suggestions added to spkgimage.c
- many small cleanups, checkpatch, FIXMEs resolved
Changes in v2:
- rewrote the stand-alone spkg_utility to integrate into mkimage
Ralph Siemsen (9):
ARM: armv7: add non-SPL enable for Cortex SMPEN
clk: renesas: prepare for non-RCAR clock
-snarc/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
---
Changes in v3:
- provide definition
Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
Changes in v3:
- rename board LCES
as existing Renesas RCAR2/3
clock drivers, using a temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
---
Changes in v3:
- convert data table to explicit reg/bit numbers
- drop the unused scon, mirack, mirstat fields
- added some kernel docs to structures
- use enum for type field
of ARCH_RZN1 symbol.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
arch/arm/Kconfig | 17 +
arch/arm/Makefile | 1 +
arch/arm/mach-rzn1/Kconfig| 18 ++
arch/arm/mach-rzn1/Makefile | 3 +++
arch/arm/mach-rzn1/cpu_info.c
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen
---
Changes in v3:
- assorted small cleanups
- support version 1.0 silicon (previously #if 0...)
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile| 2 +
drivers/ram
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
drivers/pinctrl/Makefile | 1
This is taken from Linux kernel 5.17, and contains just bare minimum
functionality: CPU, UART and system timer.
Additional functionality (from newer kernel versions) will be added
later. Note that the Linux side is under active development.
Signed-off-by: Ralph Siemsen
---
The following changes
.
The support code contains platform specific hardware access (TMU_BASE),
and it is not needed for other Renesas devices such as RZ/N1. Therefore,
alter Makefile to build renesas-cpg-mssr.c only for RCAR-GEN2/3.
Signed-off-by: Ralph Siemsen
Reviewed-by: Sean Anderson
---
Changes in v3:
- added tags
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off
On Tue, Aug 23, 2022 at 12:14:31AM -0400, Sean Anderson wrote:
Regarding the unused fields (scon, mirack, mistat): I am not really
sure what their purpose is. Maybe there is some value in having them.
I'll try to find out more information about them. If we do decide to
drop them, I would like
On Mon, Aug 22, 2022 at 11:42:54PM -0400, Sean Anderson wrote:
+static int spkgimage_check_image_types(uint8_t type)
+{
+ return type == IH_TYPE_RENESAS_SPKG ? 0 : 1;
This function is not necessary if you only support one type.
Without this function, mkimage kept telling me that my
On Tue, Aug 16, 2022 at 12:17 PM Andre Przywara wrote:
>
> So what is the story here? This commit seems to suggest U-Boot doesn't support
> even ARMv5 without "T", has this changed? There are probably other code
> places which would need adjustment to run on ARMv4?
Note that gcc 6.0 and later
, 2022 at 9:45 PM Ralph Siemsen wrote:
> >
> > I wonder if you could just fill in the header directly. This is
> > for a userspace tool, and this struct will be created at most
> > once. It's OK to use 10 bytes :)
>
> I could fill the header directly, but I figured
Hello Heinrich,
FYI, I had some trouble trying to apply your changes (patch seems to
be mangled?).
Only one small question for you, see below.
On Wed, Aug 10, 2022 at 2:42 AM Heinrich Schuchardt wrote:
>
> diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst
> index
On Sat, Aug 13, 2022 at 01:30:19AM -0400, Sean Anderson wrote:
+
+ u16 gate, reset, ready, midle,
+ scon, mirack, mistat;
What are the scon/mirack/mistat fields for? You define them for a lot
of clocks, but I don't see them used in the driver.
These came from the Linux
On Sat, Aug 13, 2022 at 10:47 AM Sean Anderson wrote:
> >
> > board/schneider/lces/spkgimage.cfg | 26 +++
> > boot/image.c | 1 +
> > include/image.h| 1 +
> > tools/Makefile | 1 +
> > tools/spkgimage.c
/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
---
Changes in v2:
- rewrote the stand-alone
On Tue, Aug 9, 2022 at 1:15 PM Sean Anderson wrote:
>
> The traditional way to handle this is to specify a config file with -n.
> See e.g. mtk_image
Thanks Pali and Sean. I have converted this tool to work as part of
mkimage, with a config file for the extra parameters. Patch v2 to
follow.
On Tue, Aug 9, 2022 at 12:07 PM Pali Rohár wrote:
>
> This documentation is not probably up-to-date. List of all kwbimage
> config options can be visible in kwbimage_generate_config() function.
I will check the code as well.
> > 1) mkimage already has far too many options
>
> I know. But for
Hi Pali,
On Tuesday 09 August 2022 15:03:48 Pali Rohár wrote:
>
> Hello! You can use for example config file, like it has kwbimage.c which
> is integrated into mkimage and has support for NAND ECC settings.
Thank you, I was unaware of this config file approach. From a quick
look at
Add support for Schneider Electronics LCES1 / LCES2 boards, which are
based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
TODO: remove the debug UART settings from
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