Wolfgang Denk schrieb:
> In message <[EMAIL PROTECTED]> you wrote:
>
>> Signed-off-by: Ricardo Ribalda Delgado <[EMAIL PROTECTED]>
>>
>
> What is the intention or practical use of this dummy driver?
>
>
>
I think we could use it well for mounting different memory
configurations on the sa
The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Please see doc/README.mvbc_p for details.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
Grant,
please have a look at v4 which additionally ad
The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Please see doc/README.mvbc_p for details.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
Grant,
please find attached v3 with further mods :
-
The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Please see doc/README.mvbc_p for details.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
Grant,
I've modified the patch to meet th
hrieb:
> On Fri, 04 Jul 2008 09:42:24 +0200
> Andre Schwarz <[EMAIL PROTECTED]> wrote:
>
> Hello Andre,
>
>
>> board/mvbc_p/fpga.c| 177
>> board/mvbc_p/fpga.h| 34
>>
>
> couldn't help but n
Kim,
thanks for the hints.
Kim Phillips schrieb:
> On Fri, 04 Jul 2008 09:42:24 +0200
> Andre Schwarz <[EMAIL PROTECTED]> wrote:
>
> Hello Andre,
>
>
>> board/mvbc_p/fpga.c| 177
>> board/mvbc_p/fpga.h| 3
Wolfgang,
thanks - I'll wait for further comments and send an update.
regards,
Andre
Wolfgang Grandegger schrieb:
> Andre Schwarz wrote:
>> The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
>> controller (using e1000) and custom Altera Cyclone-II FP
The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Please see doc/README.mvbc_p for details.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppen
Change ifdef to match "MVBC_P" board name.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
Ben,
this is a mini-patch and should do no harm.
Since MVBC_1G has gone to oblivion and the new board is named MVBC_P.
I'll submit the board patch in a few minutes.
Thanks,
I did - and e1000 no longer works.
Of course I diff'ed the network stuff - no obvious changes at all.
So I wonder if the problem is elsewhere and if e1000 is still working in
general.
As you say this is obviously true - thanks.
regards,
Andre
Wolfgang Grandegger schrieb:
> Andre
Wolfgang,
as far as I can see on the list you sent the latest patches for the
e1000 driver.
My e1000 (82541ER) stopped working on a MPC5200 based board with latest
u-boot.
I have a similar problem on another board ...
Is your e1000 working properly on the latest u-boot ?
Do I need any additional
update mvBL-M7 config file to use UBOOT_VERSION and define
CONFIG_HIGH_BATS.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Arm
Kim Phillips schrieb:
> On Wed, 02 Jul 2008 18:01:01 +0200
> Andre Schwarz <[EMAIL PROTECTED]> wrote:
>
>
>> this is a fully configured board, i.e. serial# and ethaddr/eth1addr set
>> up correctly.
>>
>> I'll give the bisect a try a soon as ther
Jerry,
I don't understand this.
The code is far from using the device tree - the dtb is fetched by tftp
right after bootp.
It's the initial bootp/dhcp that doesn't work
regards,
Andre
Jerry Van Baren schrieb:
> Kim Phillips wrote:
>> On Wed, 02 Jul 2008 16:36:1
Kim Phillips schrieb:
> On Wed, 02 Jul 2008 16:36:11 +0200
> Andre Schwarz <[EMAIL PROTECTED]> wrote:
>
>
>> Ben,
>>
>> thanks for your quick reply.
>> Looks like you're right - nothing changed regarding network yet.
>>
>> Ma
Ben,
thanks for your quick reply.
Looks like you're right - nothing changed regarding network yet.
Maybe it's a cpu specific problem.
Kim ? Can you help here ?
regards,
Andre
Ben Warren schrieb:
> Hi Andre,
>
> On Wed, Jul 2, 2008 at 7:03 AM, Andre Schwarz
> <
Ben,
after pulling u-boot today ethernet stopped working on my MPC8343 based
board (mvBL-M7).
I'm using a Vitesse VSC8601 RGMII phy on TSEC0-1.
I know there's some rewriting/clean-up going on ...
What do I have to do to get it working again ?
Any new defines introduced lately ?
Obviously the MI
Add missing #define CONFIG_HIGH_BATS in mvBL-M7 board config file.
Add default MAC to enable netboot during production.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB
*/
>
> To my config solved the problem.
>
> /Tor
>
> On 6/23/2008, "Andre Schwarz" <[EMAIL PROTECTED]> wrote:
>
>
>> Kim,
>>
>> after being back from holiday and pulling the lates u-boot today
>> (v1.3.3) my MPC8343 based board (mvBL
Kim,
after being back from holiday and pulling the lates u-boot today
(v1.3.3) my MPC8343 based board (mvBL-M7) doesn't work any longer.
Not a single character is put out on serial - yet build is not
complaining about anything and System.map looks quite normal.
Any ideas what commit can cause thi
those bits are set after reset - yet it's
unclear where they come from.
The patch keeps both bits on MPC834x and MPC8313.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 2
Add MPC8343 based board mvBlueLYNX-M7.
It's a single board stereo camera system.
Please read doc/README.mvblm7 for details.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart,
Add MPC8343 based board mvBlueLYNX-M7.
It's a single board stereo camera system.
Please read doc/README.mvblm7 for details.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart,
Martin,
thanks for the info.
The misbehaviour surely has its cause on my system setup.
I simply don't know why ... it's driving me mad.
Just wanted to port another board from my local v1.3.1 and submit a
patch during this merge window.
But the e1000 driver isn't working anymore. Making a diff gi
Wolfgang Denk schrieb:
> In message <[EMAIL PROTECTED]> you wrote:
>
>> thanks for your verification. Trying to do it your way gives :
>>
>> nova u-boot-clean # CROSS_COMPILE=ppc_6xx- sh MAKEALL TQM5200 MPC8349ITX
>> Configuring for TQM5200 board...
>> In file included from environment.c:30:
>>
Wolfgang,
thanks for your verification. Trying to do it your way gives :
nova u-boot-clean # CROSS_COMPILE=ppc_6xx- sh MAKEALL TQM5200 MPC8349ITX
Configuring for TQM5200 board...
In file included from environment.c:30:
/home/u-boot-clean/include/environment.h:107: error: 'CFG_ENV_SIZE'
undeclared
e[1]: *** [environment.o] Error 1
make[1]: Leaving directory `/home/u-boot.git/tools'
make: *** [tools] Error 2
regards,
Andre Schwarz
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Add MPC8343 based board mvBlueLYNX-M7.
It's a single board stereo camera system.
Please read doc/README.mvblm7 for details.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
--
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart,
Add MPC8343 based board mvBlueLYNX-M7.
It's a single board stereo camera system.
Please read doc/README.mvblm7 for details.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
--
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart,
Wolfgang,
thanks for the hint - unfortunately the issue is not solved, yet.
Obviously I've missed something...
U-boot is working fine with both 256MB and 512MB RAM.
The kernel crashes with memory > 256MB.
Do I need to set up a 2nd BAT for mapping main memory before booting
linux in any case ?
D
The Vitesse VSC8601 RGMII PHY has internal delay for both Rx
and Tx clock lines. They are configured using 2 bits in extended
register 0x17.
Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have
been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay.
Signed-off-by: Andre
Ben Warren schrieb:
> André Schwarz wrote:
>> Andy,
>>
>> it's no problem to re-send a "more suitable" patch as soon as Ben has
>> finished the re-work. I'll wait for him and send an updated version
>> to the list.
>>
>>
>>
> It's better to get this in now if you don't mind.
>
> regards,
> Ben
I
Andy,
thanks for your comments.
Andy Fleming schrieb:
> On Thu, Apr 24, 2008 at 9:45 AM, Andre Schwarz
> <[EMAIL PROTECTED]> wrote:
>
>
>> {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
>> +#if defined(CFG_VSC8601_SKEW_TX)
The Vitesse VSC8601 RGMII PHY has internal delay for both Rx
and Tx clock lines. They are configured using 2 bits in extended
register 0x17.
Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have
been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay.
Signed-off-by: Andre
like
I want them to be.
Setting bit 8 in "Extended PHY Control 1" @ 0x17 activates the delay lines.
Obviously your Skew values did match.
I'll send a patch to configure the delay.
Cheers,
Andre
Tor Krill schrieb:
> Hi,
>
> On 4/17/2008, "Andre Schwarz" <[E
Last week my PCI bus has been running fine showing all devices.
Right now no devices are shown on the bus.
I'm using CONFIG_83XX_GENERIC_PCI with common setup code for PCI.
Nothing changed from my side during the last 2 weeks.
Did I miss any changes in u-boot ?
regards,
Andre Schwarz
M
ards,
Andre
Kim Phillips schrieb:
On Thu, 17 Apr 2008 19:28:17 +0200
Andre Schwarz <[EMAIL PROTECTED]> wrote:
Kim,
Hello Andre,
I can't apply this:
Applying fix system config overwrite @ MPC834x
error: patch failed: cpu/mpc83xx/cpu_init.c:59
error: cpu/mpc83xx/cpu_init.c: patch
Tor,
after all my VSC8601 is up and running on MPC8343 :-)
I'm sorry to say that I don't find this patch ok after going through the
manuals :
Register 0x17 is a very coarse setting. If the capabilities of the PHY
should be taken into account and be configurable we should use the skew
contr
sing RGMII) those bits are set after reset - yet it's
unclear where they come from.
The patch keeps both bits on MPC834x.
Cheers,
Andre
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
--
cpu/mpc83xx/cpu_init.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
dif
en schrieb:
Hi Andre,
On Thu, Apr 10, 2008 at 4:37 AM, Andre Schwarz
<[EMAIL PROTECTED]> wrote:
All,
in my current system the I2C bus is not working properly on a MPC8343 in
u-boot v1.3.2.
i2c board config includes :
#define CONFIG_HARD_I2C
#undef CONFIG_SOFT_I2C
#define CONFIG_
Wolfgang,
I have indeed a LM75 on this bus - but it's not adressed.
The same I2C bus works fine on linux-2.6.25 including LM75 and EEPROM.
The oszi shows complete transactions with valid data.
I think it is as software issue.
Thanks,
Andre
[EMAIL PROTECTED] schrieb:
Hi,
On 10 Apr 2008 at 13:
Martin,
thanks for your hints.
Martin Krause schrieb:
Hi Andre,
[EMAIL PROTECTED] wrote on :
All,
in my current system the I2C bus is not working properly on a MPC8343
in
u-boot v1.3.2.
i2c board config includes :
#define CONFIG_HARD_I2C
#undef CONFIG_SOFT_I2C
#define CONFIG_FSL_I2C
ctions can
be seen on the bus.
regards,
Andre Schwarz
Matrix Vision
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Wer
MPC8343 based stereo camera system with Cyclone-II FPGA and miniPCI Slot.
CPU utilizes dual 10/100/1000 Ethernet using Vitesse VSC8601 RGMII Phys
and USB over ULPI.
512MB Micron DDR-II memory, 8MB Flash on LocalBus, SD over SPU and 32MB
NAND @ FPGA.
Signed-off-by: Andre Schwarz <[EM
Tor Krill schrieb:
On 4/3/2008, "Andre Schwarz" <[EMAIL PROTECTED]> wrote:
All,
Hi Andre and others,
currently I'm trying to bring up a mpc8343 based system.
Latest u-boot v1.3.2 is running fine.
The MPC8343 has a single 32-Bit PCI Bus running at 66MHz.
08000..0x8fff -> 0x8000 Prefetch
IO 0xe200..0xe20f -> 0x
Unable to handle kernel paging request for data at address 0x0000
Call trace gives address last called function "of_device_is_compatible".
Any help is w
Andy Fleming schrieb:
On Tue, Apr 1, 2008 at 9:08 AM, Andre Schwarz
<[EMAIL PROTECTED]> wrote:
Tor,
after investigating the tsec code I'm wondering how your PHY works in
RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into
account durin
Andy Fleming schrieb:
On Tue, Apr 1, 2008 at 8:33 AM, Andre Schwarz
<[EMAIL PROTECTED]> wrote:
Tor,
after investigating the tsec code I'm wondering how your PHY works in
RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into
account durin
Tor,
after investigating the tsec code I'm wondering how your PHY works in
RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into
account during tsec_init.
/* Init ECNTRL */
regs->ecntrl = ECNTRL_INIT_SETTINGS;
This will clear bit 27 which indicates RGMII a
let me know if you're interested.
regards,
Andre Schwarz
Matrix Vision
Kim Phillips schrieb:
On Mon, 31 Mar 2008 10:01:34 -0400
Ben Warren <[EMAIL PROTECTED]> wrote:
Tor Krill wrote:
Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII
Jerry Van Baren schrieb:
> Andre Schwarz wrote:
>> Jerry Van Baren schrieb:
>>> Andre Schwarz wrote:
>>>> In "cpu/mpc83xx/start.S" there is a comment :
>>>>
>>>> /*
>>>> * The Hard Reset Configuration Word (HRCW) table
bits wide (hardware trickery).
*/
This does _not_ hold true for all configurations. Flash is simply one of
many options ...
Maybe it's true for the Freescale boards.
Other sources of the HRCW can be hard-coded strapping pins or an I2C EEPROM.
Why is there a need to define the HRCW ?
Kim Phillips schrieb:
On Tue, 25 Mar 2008 21:25:45 +0100
Andre Schwarz <[EMAIL PROTECTED]> wrote:
I've seen things like this in mpc8349emds code :
#if (CFG_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
Is this reasonable ? Why ?
Kim Phillips schrieb:
On Tue, 25 Mar 2008 20:41:41 +0100
Andre Schwarz <[EMAIL PROTECTED]> wrote:
Kim Phillips schrieb:
On Tue, 25 Mar 2008 18:36:47 +0100
Andre Schwarz <[EMAIL PROTECTED]> wrote:
As far as I can see there are only DDR-I boards fr
Kim Phillips schrieb:
On Tue, 25 Mar 2008 18:36:47 +0100
Andre Schwarz <[EMAIL PROTECTED]> wrote:
All,
has anyone set up the DDR-II controller on a Freescale MPC8343A without ?
without what?
typo - sorry.
As far as I can see there are only DDR-I boards from Fre
All,
has anyone set up the DDR-II controller on a Freescale MPC8343A without ?
As far as I can see there are only DDR-I boards from Freescale.
Are there any patches not yet posted to handle this ?
regards,
Andre Schwarz
Matrix Vision
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler
Grant Likely schrieb:
On Thu, Mar 13, 2008 at 6:50 AM, André Schwarz
<[EMAIL PROTECTED]> wrote:
include fec specific nodes in ft_cpu_setup only if CONFIG_MPC5xxx_FEC is
defined. Systems without FEC, i.e. no fec node in dtb, should be possible.
Signed-off-by: Andre Schwarz &
Heiko Schocher schrieb:
Hello Stefan,
Stefan Roese wrote:
On Thursday 06 March 2008, Andre Schwarz wrote:
Stefan Roese schrieb:
On Wednesday 05 March 2008, Andre Schwarz wrote:
[...]
There's a include/ACEX1K.h that introduces two interfaces for obviously
the
Add 82541ER device with latest integrated IGP2 PHY.
Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB
Add 82541ER device with latest integrated IGP2 PHY.
Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom.
regards,
Andre Schwarz
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner
ation. This code can't work.
Is there any interest in getting this fixed ?
What about Liberty's Stratix code ? It's living and working !
regards,
Andre Schwarz
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergeric
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