Module Name:    src
Committed By:   jmcneill
Date:           Fri Dec  5 18:41:41 UTC 2014

Modified Files:
        src/sys/arch/arm/allwinner: awin_gige.c awin_io.c awin_reg.h awin_var.h

Log Message:
Partial A80 GMAC support. Needs help from PMU to power it up still.


To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/allwinner/awin_gige.c
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/arm/allwinner/awin_io.c
cvs rdiff -u -r1.62 -r1.63 src/sys/arch/arm/allwinner/awin_reg.h
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/allwinner/awin_var.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/allwinner/awin_gige.c
diff -u src/sys/arch/arm/allwinner/awin_gige.c:1.19 src/sys/arch/arm/allwinner/awin_gige.c:1.20
--- src/sys/arch/arm/allwinner/awin_gige.c:1.19	Sun Nov 23 23:05:19 2014
+++ src/sys/arch/arm/allwinner/awin_gige.c	Fri Dec  5 18:41:41 2014
@@ -31,7 +31,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: awin_gige.c,v 1.19 2014/11/23 23:05:19 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_gige.c,v 1.20 2014/12/05 18:41:41 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -69,6 +69,9 @@ static const struct awin_gpio_pinset awi
 	'A', AWIN_A31_PIO_PA_GMAC_FUNC, AWIN_A31_PIO_PA_GMAC_PINS, 0, 3
 };
 
+static const struct awin_gpio_pinset awin_gige_gpio_pinset_a80 = {
+	'A', AWIN_A80_PIO_PA_GMAC_FUNC, AWIN_A80_PIO_PA_GMAC_PINS, 0, 3
+};
 
 CFATTACH_DECL_NEW(awin_gige, sizeof(struct awin_gige_softc),
 	awin_gige_match, awin_gige_attach, NULL, NULL);
@@ -102,12 +105,26 @@ awin_gige_attach(device_t parent, device
 	struct awin_gige_softc * const sc = device_private(self);
 	struct awinio_attach_args * const aio = aux;
 	const struct awin_locators * const loc = &aio->aio_loc;
-	struct awin_gpio_pinset pinset =
-	    awin_chip_id() == AWIN_CHIP_ID_A31 ?
-	    awin_gige_gpio_pinset_a31 : awin_gige_gpio_pinset;
+	struct awin_gpio_pinset pinset;
 	prop_dictionary_t cfg = device_properties(self);
 	uint32_t clkreg;
 	const char *phy_type, *pin_name;
+	bus_space_handle_t bsh;
+
+	switch (awin_chip_id()) {
+	case AWIN_CHIP_ID_A80:
+		bsh = aio->aio_a80_core2_bsh;
+		pinset = awin_gige_gpio_pinset_a80;
+		break;
+	case AWIN_CHIP_ID_A31:
+		bsh = aio->aio_core_bsh;
+		pinset = awin_gige_gpio_pinset_a31;
+		break;
+	default:
+		bsh = aio->aio_core_bsh;
+		pinset = awin_gige_gpio_pinset;
+		break;
+	}
 
 	sc->sc_core.sc_dev = self;
 
@@ -116,7 +133,7 @@ awin_gige_attach(device_t parent, device
 
 	sc->sc_core.sc_bst = aio->aio_core_bst;
 	sc->sc_core.sc_dmat = aio->aio_dmat;
-	bus_space_subregion(sc->sc_core.sc_bst, aio->aio_core_bsh,
+	bus_space_subregion(sc->sc_core.sc_bst, bsh,
 	    loc->loc_offset, loc->loc_size, &sc->sc_core.sc_bsh);
 
 	aprint_naive("\n");
@@ -147,10 +164,14 @@ awin_gige_attach(device_t parent, device
 	/*
 	 * Enable GMAC clock
 	 */
-	if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+	if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+		    AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_REG,
+		    AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_GMAC, 0);
+	} else if (awin_chip_id() == AWIN_CHIP_ID_A31) {
 		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
 		    AWIN_AHB_GATING0_REG, AWIN_A31_AHB_GATING0_GMAC, 0);
-	} else {
+	} else if (awin_chip_id() == AWIN_CHIP_ID_A20) {
 		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
 		    AWIN_AHB_GATING1_REG, AWIN_AHB_GATING1_GMAC, 0);
 	}
@@ -158,9 +179,14 @@ awin_gige_attach(device_t parent, device
 	/*
 	 * Soft reset
 	 */
-	if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+	if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+		    AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_REG,
+		    AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_GMAC, 0);
+	} else if (awin_chip_id() == AWIN_CHIP_ID_A31) {
 		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
-		    AWIN_A31_AHB_RESET0_REG, AWIN_A31_AHB_RESET0_GMAC_RST, 0);
+		    AWIN_A31_AHB_RESET0_REG,
+		    AWIN_A31_AHB_RESET0_GMAC_RST, 0);
 	}
 
 	/*
@@ -184,7 +210,11 @@ awin_gige_attach(device_t parent, device
 	} else {
 		panic("unknown phy type '%s'", phy_type);
 	}
-	if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+	if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+		awin_reg_set_clear(aio->aio_core_bst, aio->aio_a80_core2_bsh,
+		    AWIN_A80_SYS_CTRL_OFFSET + AWIN_A80_SYS_CTRL_EMAC_CLK_REG,
+		    clkreg, AWIN_GMAC_CLK_PIT|AWIN_GMAC_CLK_TCS);
+	} else if (awin_chip_id() == AWIN_CHIP_ID_A31) {
 		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
 		    AWIN_A31_GMAC_CLK_REG, clkreg,
 		    AWIN_GMAC_CLK_PIT|AWIN_GMAC_CLK_TCS);

Index: src/sys/arch/arm/allwinner/awin_io.c
diff -u src/sys/arch/arm/allwinner/awin_io.c:1.34 src/sys/arch/arm/allwinner/awin_io.c:1.35
--- src/sys/arch/arm/allwinner/awin_io.c:1.34	Fri Dec  5 17:32:08 2014
+++ src/sys/arch/arm/allwinner/awin_io.c	Fri Dec  5 18:41:41 2014
@@ -31,7 +31,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.34 2014/12/05 17:32:08 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.35 2014/12/05 18:41:41 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -56,6 +56,7 @@ static struct awinio_softc {
 	bus_space_handle_t sc_bsh;
 	bus_space_handle_t sc_ccm_bsh;
 	bus_space_handle_t sc_a80_usb_bsh;
+	bus_space_handle_t sc_a80_core2_bsh;
 	bus_dma_tag_t sc_dmat;
 	bus_dma_tag_t sc_coherent_dmat;
 } awinio_sc;
@@ -168,6 +169,7 @@ static const struct awin_locators awin_l
 	{ "awe", OFFANDSIZE(EMAC), NOPORT, AWIN_IRQ_EMAC, A10|A20 },
 	{ "awge", OFFANDSIZE(GMAC), NOPORT, AWIN_IRQ_GMAC, A20 },
 	{ "awge", OFFANDSIZE(A31_GMAC), NOPORT, AWIN_A31_IRQ_GMAC, A31 },
+	{ "awge", OFFANDSIZE(A80_GMAC), NOPORT, AWIN_A80_IRQ_EMAC, A80 },
 	{ "awincrypto", OFFANDSIZE(SS), NOPORT, AWIN_IRQ_SS, AANY },
 	{ "awinac", OFFANDSIZE(AC), NOPORT, AWIN_IRQ_AC, A10|A20 },
 	{ "awinac", OFFANDSIZE(AC), NOPORT, AWIN_A31_IRQ_AC, A31 },
@@ -219,6 +221,8 @@ awinio_attach(device_t parent, device_t 
 		    AWIN_A80_CCU_SCLK_OFFSET, 0x1000, &sc->sc_ccm_bsh);
 		bus_space_map(sc->sc_bst, AWIN_A80_USB_PBASE,
 		    AWIN_A80_USB_SIZE, 0, &sc->sc_a80_usb_bsh);
+		bus_space_map(sc->sc_bst, AWIN_A80_CORE2_PBASE,
+		    AWIN_A80_CORE2_SIZE, 0, &sc->sc_a80_core2_bsh);
 		break;
 	default:
 		bus_space_subregion(sc->sc_bst, sc->sc_bsh, AWIN_CCM_OFFSET,
@@ -266,6 +270,7 @@ awinio_attach(device_t parent, device_t 
 			.aio_core_bsh = sc->sc_bsh,
 			.aio_ccm_bsh = sc->sc_ccm_bsh,
 			.aio_a80_usb_bsh = sc->sc_a80_usb_bsh,
+			.aio_a80_core2_bsh = sc->sc_a80_core2_bsh,
 			.aio_dmat = sc->sc_dmat,
 			.aio_coherent_dmat = sc->sc_coherent_dmat,
 		};

Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.62 src/sys/arch/arm/allwinner/awin_reg.h:1.63
--- src/sys/arch/arm/allwinner/awin_reg.h:1.62	Fri Dec  5 17:32:08 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h	Fri Dec  5 18:41:41 2014
@@ -2695,6 +2695,12 @@ struct awin_a31_dma_desc {
 #define AWIN_A80_USB2_OFFSET		0x00002000
 #define AWIN_A80_USBPHY_OFFSET		0x00008000
 
+/*
+ * These offsets are relative to AWIN_A80_CORE2_PBASE
+ */
+#define AWIN_A80_SYS_CTRL_OFFSET	0x00000000
+#define AWIN_A80_GMAC_OFFSET		0x00030000
+
 #define AWIN_A80_SDMMC_COMM_SDC_RESET_SW	__BIT(18)
 #define AWIN_A80_SDMMC_COMM_SDC_CLOCK_SW	__BIT(16)
 
@@ -2742,6 +2748,7 @@ struct awin_a31_dma_desc {
 
 #define AWIN_A80_CCU_SCLK_BUS_CLK_GATING0_SD	__BIT(8)
 
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_GMAC	__BIT(17)
 #define AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_USB_HOST __BIT(1)
 
 #define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI4	__BIT(4)
@@ -2752,6 +2759,7 @@ struct awin_a31_dma_desc {
 
 #define AWIN_A80_CCU_SCLK_BUS_SOFT_RST0_SD	__BIT(8)
 
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_GMAC	__BIT(17)
 #define AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_USB_HOST __BIT(1)
 
 #define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI4	__BIT(4)
@@ -2790,7 +2798,13 @@ struct awin_a31_dma_desc {
 #define AWIN_A80_USBPHY_HCI_PCR_480M_GATING_HCI1_HSIC __BIT(2)
 #define AWIN_A80_USBPHY_HCI_PCR_SCLK_GATING_HCI0_PHY __BIT(1)
 
+#define AWIN_A80_SYS_CTRL_VER_REG		0x0024
+#define AWIN_A80_SYS_CTRL_EMAC_CLK_REG		0x0030
+#define AWIN_A80_SYS_CTRL_DISP_MUX_CTRL_REG	0x0038
+
 #define AWIN_A80_PIO_PA_PINS		18
+#define AWIN_A80_PIO_PA_GMAC_FUNC	2
+#define AWIN_A80_PIO_PA_GMAC_PINS	0x0003f7bf /* PA pins 17-12,10-7,5-0 */
 
 #define AWIN_A80_PIO_PB_PINS		20
 #define AWIN_A80_PIO_PB_TWI4_FUNC	4

Index: src/sys/arch/arm/allwinner/awin_var.h
diff -u src/sys/arch/arm/allwinner/awin_var.h:1.30 src/sys/arch/arm/allwinner/awin_var.h:1.31
--- src/sys/arch/arm/allwinner/awin_var.h:1.30	Fri Dec  5 17:32:08 2014
+++ src/sys/arch/arm/allwinner/awin_var.h	Fri Dec  5 18:41:41 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_var.h,v 1.30 2014/12/05 17:32:08 jmcneill Exp $ */
+/* $NetBSD: awin_var.h,v 1.31 2014/12/05 18:41:41 jmcneill Exp $ */
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -60,6 +60,7 @@ struct awinio_attach_args {
 	bus_space_handle_t aio_core_bsh;
 	bus_space_handle_t aio_ccm_bsh;
 	bus_space_handle_t aio_a80_usb_bsh;
+	bus_space_handle_t aio_a80_core2_bsh;
 	bus_dma_tag_t aio_dmat;
 	bus_dma_tag_t aio_coherent_dmat;
 };

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