2011-07-19 00:07 keltezéssel, Mike Frysinger írta:
2011/7/18 Márton Miklós:
in the future, please attach patches to your e-mail instead of posting
random URLs
Sorry, but last time when I did it my mail was rejected due the large
attachment.
both patches you posted were less than 100KiB
The bypass flash write method should work for everyone who is using these
flashes.
To understood the latch patch better I attach the related part of my
schematic.
The SOC has a 64 bit wide port which is used as address, and data bus too.
At the beginning of a bus-cycle it outputs the address to this bus while
LALE is active, then turn off the latch, and then outputs the data.
This takes 3 BSR shift. If the address did not changes between two cycle the
latching is unneccessary for everyone who is using muxed bus.
ok, i think the issue is that you squashed two changes into one patch.
please split them out into independent patches so things will be
clear.
--- src/flash/amd.c (revision 1966)
+++ src/flash/amd.c (working copy)
+int bypass_supported = 0;
global variables are not acceptable. you can initialize multiple
buses simultaneously and this global variable would break that.
What would you recommend to share data between the flash_printinfo and the
other flash functions?
seems like you want to extend URJ_FLASH_CFI_ARRAY in src/flash/flash.h
-mike
Hello,
I have separated my patches and I hope that my code is now follows the
conventions.
The bypass.patch adds support for the S29AL032* flashes bypass program
method.
The mpc837x.patch improves the programming speed via the mpc837x bus
using the bypass flashing method.
Regards,
Miklós
Index: urjtag/src/flash/amd.c
===================================================================
--- urjtag/src/flash/amd.c (revision 1979)
+++ urjtag/src/flash/amd.c (working copy)
@@ -29,6 +29,8 @@
* August 14, 2001 Rev A, 25022.pdf
* [3] Spansion, "S29GL-N MirrorBit Flash Family"
* October 13, 2006 Rev B, Amendment 3
+ * [4] Spansion, "S29AL032D 32 Megabit CMOS 3.0 Volt-only Flash Memory" datasheet
+ * September 21, 2005 Rev A, Amendment 5
*
*/
@@ -300,6 +302,7 @@
int mid, cid, prot;
urj_bus_t *bus = cfi_array->bus;
int o = amd_flash_address_shift (cfi_array);
+ cfi_array->amd_bypass_supported = 0;
URJ_BUS_WRITE (bus, cfi_array->address + (0x0555 << o), 0x00aa00aa); /* autoselect p29 */
URJ_BUS_WRITE (bus, cfi_array->address + (0x02aa << o), 0x00550055);
@@ -335,6 +338,26 @@
case 0x007E: /* 8-bit mode */
urj_log (ll, "S92GLxxxN");
break;
+ case 0x00A3:
+ cfi_array->amd_bypass_supported = 1;
+ urj_log (ll, "S29AL032D model 00");
+ break;
+ case 0xF6:
+ cfi_array->amd_bypass_supported = 1;
+ urj_log (ll, "S29AL032D model 03 byte mode");
+ break;
+ case 0x22F6:
+ cfi_array->amd_bypass_supported = 1;
+ urj_log (ll, "S29AL032D model 03 word mode");
+ break;
+ case 0x00F9:
+ cfi_array->amd_bypass_supported = 1;
+ urj_log (ll, "S29AL032D model 04 byte mode");
+ break;
+ case 0x22F9:
+ cfi_array->amd_bypass_supported = 1;
+ urj_log (ll, "S29AL032D model 04 word mode");
+ break;
default:
urj_log (ll, _("Unknown (ID 0x%04x)"), cid);
break;
@@ -588,6 +611,42 @@
}
static int
+amd_flash_program_bypass (urj_flash_cfi_array_t *cfi_array, uint32_t adr,
+ uint32_t *buffer, int count)
+{
+ int o = amd_flash_address_shift (cfi_array);
+ int offset = 0;
+ urj_bus_t *bus = cfi_array->bus;
+
+ urj_log (URJ_LOG_LEVEL_DETAIL, "amd_flash_program_bypass 0x%08lX, count 0x%08X\n",
+ (long unsigned) adr, count);
+
+ /* Execute the Unlock Bypass Command */
+ URJ_BUS_WRITE (bus, cfi_array->address + (0x0555 << o), 0x00aa00aa);
+ URJ_BUS_WRITE (bus, cfi_array->address + (0x02aa << o), 0x00550055);
+ URJ_BUS_WRITE (bus, cfi_array->address + (0x0555 << o), 0x00200020);
+
+ while (count > 0)
+ {
+ urj_log (URJ_LOG_LEVEL_DEBUG, "flash_program using unlock bypass 0x%08lX = 0x%08lX\n",
+ (long unsigned) adr, (long unsigned) buffer[offset]);
+ URJ_BUS_WRITE (bus, adr, 0x00a000a0);
+ URJ_BUS_WRITE (bus, adr, buffer[offset]);
+ adr += cfi_array->bus_width;
+ offset++;
+ count--;
+ }
+
+ urj_log (URJ_LOG_LEVEL_DETAIL, "unlock bypass reset\n");
+
+ /* Unlock Bypass Reset Command */
+ URJ_BUS_WRITE (bus, 0, 0x00900090);
+ URJ_BUS_WRITE (bus, 0, 0x00000000);
+
+ return URJ_STATUS_OK;
+}
+
+static int
amd_flash_program (urj_flash_cfi_array_t *cfi_array, uint32_t adr,
uint32_t *buffer, int count)
{
@@ -598,6 +657,12 @@
max_bytes_write = 1;
#endif
+ if (cfi_array->amd_bypass_supported == 1)
+ {
+ return amd_flash_program_bypass(cfi_array, adr, buffer, count);
+ }
+
+
/* multi-byte writes supported? */
if (max_bytes_write > 1) {
int result;
Index: urjtag/src/flash/flash.h
===================================================================
--- urjtag/src/flash/flash.h (revision 1979)
+++ urjtag/src/flash/flash.h (working copy)
@@ -50,6 +50,7 @@
uint32_t address;
int bus_width; /* in cfi_chips, e.g. 4 for 32 bits */
urj_flash_cfi_chip_t **cfi_chips;
+ int amd_bypass_supported;
};
extern urj_flash_cfi_array_t *urj_flash_cfi_array;
Index: urjtag/src/bus/mpc837x.c
===================================================================
--- urjtag/src/bus/mpc837x.c (revision 1979)
+++ urjtag/src/bus/mpc837x.c (working copy)
@@ -44,6 +44,7 @@
typedef struct {
uint32_t last_adr;
+ uint32_t last_write_adr;
urj_part_signal_t *nlcs[LBC_NUM_LCS];
urj_part_signal_t *lad[LBC_NUM_LAD];
urj_part_signal_t *la[LBC_NUM_LAD];
@@ -92,6 +93,7 @@
bp->lbc_muxed = 0;
bp->lbc_num_d = 8;
bp->lbc_num_ad = 25;
+ bp->last_write_adr = UINT32_MAX;
for (i = 0; cmd_params[i] != NULL; i++)
{
@@ -452,10 +454,14 @@
if (bp->lbc_muxed)
{
setup_address (bus, adr);
- urj_part_set_signal (p, ALE, 1, 1);
- urj_tap_chain_shift_data_registers (chain, 0);
- urj_part_set_signal (p, ALE, 1, 0);
- urj_tap_chain_shift_data_registers (chain, 0);
+ if (bp->last_write_adr != adr) /* latch is unneccessary if the address did not changed */
+ {
+ bp->last_write_adr = adr;
+ urj_part_set_signal (p, ALE, 1, 1);
+ urj_tap_chain_shift_data_registers (chain, 0);
+ urj_part_set_signal (p, ALE, 1, 0);
+ urj_tap_chain_shift_data_registers (chain, 0);
+ }
}
else
setup_address (bus, adr);
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