Re: [coreboot] coreboot is going to make kcma-d8 obsolete

On Sat, Apr 07, 2018 at 02:25:19PM +0100, Leah Rowe wrote: > If you've got a D16 to submit reports on, that'd also be great. I just pushed one on the D16. Thanks, Ward. -- Ward Vandewege GPG Key: 25F774AB Do you use free software? Donate to join the FSF and support freedom at h

[coreboot] OpenBMC/iKVM4 on KGPE-D16: bmc doesn't power up automatically on cold boot

issue? Thanks, Ward. -- Ward Vandewege GPG Key: 25F774AB Do you use free software? Donate to join the FSF and support freedom at http://www.fsf.org/register_form?referrer=859 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] kexec of Xen hypervisor from a Linux payload

; My 4.6.3 Xen tree is hacked up right now with stuff copied from old > versions of the tree, so I'll clean it up and see if they are interested > in accepting patches. Oh, wow, thank you! Sorry that I didn't spend time tracking that down properly back in 2008. I'd be interested to know if Xen tak

Re: [coreboot] coreboot ported to the ASUS KGPE-D16 (Libreboot: blobless, fully functional!)

On Wed, Apr 29, 2015 at 10:46:29PM +0100, The Gluglug wrote: You should crowd-fund the $35,000 figure, there are lots of people who will be interested in this. I personally will chip in, and I'd ask others to as well. I would chip in too. Thanks, Ward. -- Ward Vandewege GPG Key: 25F774AB

Re: [coreboot] Are any Chromebooks able to run fully libre?

on the Asus F2A85-M/CSM board. You can also omit the optional xhci blob (no usb3 support) as well as the VGA BIOS. Thanks, Ward. -- Ward Vandewege GPG Key: 25F774AB Do you use free software? Donate to join the FSF and support freedom at http://www.fsf.org/register_form?referrer=859

Re: [coreboot] DDR fails on F2A85-M

41 00 00 00 |AGESA...| 206210-007acd50 56 31 2e 31 2e 30 2e 37 20 20 20 20 00 00 00 00 |V1.1.0.7 | Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://status.fsf.org/ward http://fsf.org/blogs/RSS | http://identi.ca/cure

Re: [coreboot] DDR fails on F2A85-M

On Wed, May 22, 2013 at 11:18:46AM -0400, Ward Vandewege wrote: However, hd/strings suggest that the AGESA version is v1.1.0.7: 206209:007acd40 00 00 00 00 30 30 30 30 41 47 45 53 41 00 00 00 |AGESA...| 206210-007acd50 56 31 2e 31 2e 30 2e 37 20 20 20 20 00 00 00 00 |V1.1.0.7

[coreboot] server board support - Supermicro H8DGi-F ?

issue with AGESA 1.0.3. Anyone else interested in working on a port of H8DGi-F or a similar board? Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS Do you use free software? Donate to join the FSF and support

Re: [coreboot] Gerrit problem: Not able to sign in

. Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS Do you use free software? Donate to join the FSF and support freedom at http://www.fsf.org/register_form?referrer=859 -- coreboot mailing list: coreboot

Re: [coreboot] [SPAM] Re: Feedback On Coreboot: the Solution to the SecureBoot Fiasco

On Mon, Jan 07, 2013 at 03:29:01PM +0100, Xavi Drudis Ferran wrote: For now secure boot only restricts what we boot (and the booted OS restricts the rest of what we run). But in the end the purpuse is to stablish a DRM scheme so that if a server can't prove that we're running software

Re: [coreboot] tyan s2882-d not booting

grep the git log for the svn revision number (it is listed); you'll see these are revisions from 2006. I do have an s2881 that I booted succesfully about 5 or 6 weeks ago, with coreboot head. It's a very similar board. Have you tried with less ram? Thanks, Ward. -- Ward Vandewege | CTO, Free

Re: [coreboot] Moving gerrit to an separate mailing list

all agree. I very much agree. Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS Do you use free software? Donate to join the FSF and support freedom at http://www.fsf.org/register_form?referrer=859

Re: [coreboot] New Motherboards?

Delta 1010s. Finding a modern board with two 'old' PCI slots may be difficult, regardless of coreboot... Have you seen any at all? Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS Do you use free software? Donate

Re: [coreboot] separate mailling list for gerrit mails?

On Sun, Mar 11, 2012 at 10:19:41PM -0400, Kevin O'Connor wrote: I'd prefer if they were on a separate email list. Me, too. Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS Do you use free software? Donate

Re: [coreboot] Coreboot meeting @ Google, Sunday Mar. 13

hardware, but we've never had any (real) trouble with that approach when trying this in Brussels, Denver or Hamburg. :-) Well, in Hamburg they were a bit upset about this after about three consecutive evenings of hacking in the hotel lobby. Ah, well. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free

Re: [coreboot] Fam10 FIDVID in SVI : disabling microcode update

Hi Xavi, On Wed, Feb 16, 2011 at 02:45:02PM +0100, Xavi Drudis Ferran wrote: Should I send a patch making a Kconfig option to not upgrade microcode for fam10? Is there any interest in that ? Yes, please. I would test and ack that. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free

[coreboot] enabling expert mode - build fails (warnings treated as errors) on fam10 boards

but in the checks in h3finit.c. What's the best way to fix this? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] don't print too early on mcp55-based boards

On Mon, Nov 01, 2010 at 11:01:41PM +0100, Peter Stuge wrote: Ward Vandewege wrote: See attached. Perhaps we should also print a post code if the SMBus controller can't be found - suggestions for a value? 0x5B ? Let's do that as part of the die modification. We can't print this early

Re: [coreboot] [PATCH]Move QRANK_DIMM_SUPPORT to Kconfig

/ProductList.aspx?Submit=ENEDEPA=0Order=BESTMATCHDescription=ddr3+quad+rankx=0y=0 Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] don't print too early on mcp55-based boards

runtime error conditions would be a) set a unique post code b) call die in the assumption that die does not clobber the post code. What do you think? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot

[coreboot] [PATCH] don't print too early on mcp55-based boards

See attached. Perhaps we should also print a post code if the SMBus controller can't be found - suggestions for a value? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator We can't print this early. This patch fixes a hang on supermicro

Re: [coreboot] [PATCH] Gigabyte MA785GMT support

. See http://www.coreboot.org/GIGABYTE_GA-MA785GMT-UD2H Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Simplify device enabling and initialization

there is an ADM1027 on your board. Is there something missing before an Ack commit? I think it's good. Thanks for writing the patches! Acked-by: Ward Vandewege w...@gnu.org Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] [PATCH] Simplify device enabling and initialization

to be cold booted in order for the initialization to be needed? All boots were cold. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Simplify device enabling and initialization

On Mon, Jun 21, 2010 at 07:36:39AM -0600, Myles Watson wrote: On Mon, Jun 21, 2010 at 5:59 AM, Myles Watson myle...@gmail.com wrote: On Sun, Jun 20, 2010 at 8:11 PM, Ward Vandewege w...@gnu.org wrote: Hi Myles, Everything seems fine with either patch - but there are some differences

Re: [coreboot] [PATCH] Simplify device enabling and initialization

), r5635 + patch 1 and r5635 + patch 2. Let me know if you need anything else... Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Simplify device enabling and initialization

(the guts) of an s2881 lying on my desk here, and can test any patches you throw at me :) Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [h8dme-fam10] acquiring coreboot skills from scratch somewhat daunting

each memory write is timing out so a bunch of writes via memset drags the total timeout to an hour. At that point we try to load the payload so it seems that I am really really close to the end here It does sound like it. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software

Re: [coreboot] Indtast Bcc Indtast Bcc Wyse S10 and coreboot

package that refers to libpci-dev in Lucid. I've put a note to that effect on the wiki, too. Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] FILO bug disk not seen at ata-0 (Doesn't try to detect on ATA only SIL3114)

-by: Ward Vandewege w...@gnu.org Thanks! Ward. On Sun, May 09, 2010 at 12:33:50AM +0200, Rudolf Marek wrote: The sil3114 chip has a class code set to something else then IDE by strap resistor. It took me long time to figure out that this chip is otherwise IDE compatible ;) Try attached patch

Re: [coreboot] H8DME-2 woes, hints?

, and try to put together an h8dme_fam10 port. For the record, I've been trying to get that going for a while, but have not had much success - very early hangs in the fam10 code on this board. Cf. the problems Knut is having, I think... Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software

Re: [coreboot] Query, known-good CPUs to use in a H8DME-2 mb?

, with a pair of model # CPUs, which are of the K8 line. The port for that board was done on a pair of 2216 HE CPUs. You may be hard pressed to find those for sale these days... Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot

Re: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard

to bring it up, since using a linux kernel as a payload has worked for me in the past. Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] H8QME-2+ boot problems on different machines.

? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] warning days - m57sli/mcp55

and stop deleting them :-) I'll not add any new ones then! Updated patch attached. I see the ACPI warnings were already fixed in another commit. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator This fixes a number of warnings when building

[coreboot] [PATCH] warning days - m57sli/mcp55

If there are better ways to kill the warnings, please let me know! Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator This fixes a number of warnings when building m57sli (and other boards with mcp55). This patch is boot tested on m57sli

Re: [coreboot] [PATCH]: AMD RS780/SB700 support

is DDR3 - didn't Zheng say that was not supported with fam10 CPUs yet? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator Join us in Cambridge for LibrePlanet, March 19th-21st! http://groups.fsf.org/wiki/LibrePlanet2010 -- coreboot mailing list

Re: [coreboot] Supermicro H8QME-2+ mct_d fatal exit.

successfully start with coreboot. But when I start with coreboot and fail with mcr_d fatal exit those registers are blank, I know that because I found a nice piece of code dumping smbus registers on the h8dme board :D thx to the autor!! That would have been Marc Jones :) Thanks, Ward. -- Ward

Re: [coreboot] Un-brick a GAM57SLIS4

, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator Join us in Cambridge for LibrePlanet, March 19th-21st! http://groups.fsf.org/wiki/LibrePlanet2010 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Hi...all

. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] server hardware without IPMI / with coreboot

might be possible. This chipset is likely to be around for a while (5 years?). Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] More lists

On Tue, Feb 23, 2010 at 10:47:21AM -0700, Myles Watson wrote: Could we have some tag to svn commit like: And then add: current-works And also the haha this is broken tag and maybe the will fry your mainboard tag. :) One problem is that commits that are board-specific hopefully

Re: [coreboot] Tester hardware

On Wed, Feb 24, 2010 at 12:14:30AM +0100, Carl-Daniel Hailfinger wrote: On 23.02.2010 21:14, Peter Stuge wrote: Ward Vandewege wrote: The automatic testing framework Stepan built a few years ago - I'd love to get a few boards set up for that. I have some boards lying around

[coreboot] [PATCH] fix Tyan s2881 boot (Kconfig)

This fixes breakage introduced in r5051. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator Revision 5051 broke Kconfig booting for the Tyan s2881 board. Up to 5050, there were two SB_HT_CHAIN_ON_BUS0 sections in the mainboard Kconfig file

Re: [coreboot] [PATCH] fix Tyan s2881 boot (Kconfig)

On Wed, Feb 03, 2010 at 06:52:57PM +0100, Stefan Reinauer wrote: On 2/3/10 6:50 PM, Ward Vandewege wrote: This fixes breakage introduced in r5051. Thanks, Ward. Sorry for the inconvenience. Acked-by: Stefan Reinauer ste...@coresystems.de No worries - fixed in r5083 for both

[coreboot] dell server BIOS setting insanity

Hi all, I thought I'd point out this little gem from the linux-poweredge list http://lists.us.dell.com/pipermail/linux-poweredge/2010-January/041170.html Apparently several lines of Dell servers have a BIOS setting called Cores-per-processor. It seems they ship these machines with the

Re: [coreboot] Memtest86+ failing on coreboot system.

? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] fam10/newconfig on supermicro h8dme - early hang

, and the Routing Table Disable bit is set to zero. You mentioned bit 11 - that seems to be marked as 'reserved' in the BKDG for fam10? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org

Re: [coreboot] Problems porting H8dmr_fam10 to H8qme-2+

if I comment out that if/endif lines and have CONFIG_LOGICAL_CPUS set to zero. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] fam10/newconfig on supermicro h8dme - early hang

/mcp55_early_setup_car.c Log attached. Anything else I should try? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator minicom-20091222aa-all-ram-on-cpu1.cap Description: application/cap -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] fam10/newconfig on supermicro h8dme - early hang

the k8/util.c code. Right. I've done that - log attached. I'm dumping with showallroutes(BIOS_DEBUG, PCI_DEV(0, 0x18, 1)); I'm not sure what to make of the dump though (attached). Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator

Re: [coreboot] fam10/newconfig on supermicro h8dme - early hang

is this -MMIO(b8)00-31a4f2, -(0,1), , , CPU disable 0, Lock 0, Non posted 0 +MMIO(b8)00-31a6b2, -(0,1), , , CPU disable 0, Lock 0, Non posted 1 which may be entirely unrelated? I'll look at that other register tomorrow. Thanks! Ward. -- Ward Vandewege w...@fsf.org Free Software

[coreboot] fam10/newconfig on supermicro h8dme - early hang

://ward.vandewege.net/coreboot/h8dme/fam10/src-mainboard-supermicro-h8dme_fam10.tgz http://ward.vandewege.net/coreboot/h8dme/fam10/targets-supermicro-h8dme_fam10.tgz Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot

Re: [coreboot] coreboot hangs on my AMD fam10 board(updatedebugmessage).

that help? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [v2] r4886 - in trunk/coreboot-v2/util: . amdtools amdtools/example_input

. What's our current thinking on that? I'd be happy to svn move them... Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]

. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Resend: [PATCH] add h8dmr fam10 target

On Tue, Sep 22, 2009 at 03:29:05PM +0200, Peter Stuge wrote: Ward Vandewege wrote: Add supermicro h8dmr fam10 target. This is largely a mashup of the tyan s2912 fam10 and h8dmr k8 targets. Many, many thanks to Marc, Myles, Patrick and Stepan for all their help with this, and to Arne

Re: [coreboot] Resend: [PATCH] add h8dmr fam10 target

testing on this hardware, but it's in production so that's a little hard right now. I'm going to work on a supermicro h8dme fam10 port now, which is a very similar board, so hopefully I'll be able to try the suggestions in this thread on that. Thanks! Ward. -- Ward Vandewege w...@gnu.org

Re: [coreboot] GPIOs on CS5536 based boards

the msr and then do the right thing, but it does not. I think Peter Stuge may have a patch for the LED driver... Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] GPIOs on CS5536 based boards

prefer the driver not make assumptions for no da^Wreason. I think the driver assumes CS5536_BASE = 0x06100 Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] Tyan s2881 Kconfig

/product.asp?id=847374 Argh, can not resist. Ordered :) Good for spare parts, too - I've still got a couple of those out in the field... Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] unstable AMD Fam10h boot

be able to test this in a couple days. Will do as soon as we get the hardware. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] unstable AMD Fam10h boot

matters even further, but since we are talking about locking - will any of this improve the 'many cores talking to serial at once' problem? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] PATCH: do not rely on tempfile being available

On Wed, Sep 02, 2009 at 04:12:21PM -0400, Bernie Innocenti wrote: Signed-off-by: Bernie Innocenti ber...@codewiz.org Build fix: add a fallback for systems where tempfile is missing Acked-by: Ward Vandewege w...@gnu.org Committed in r271. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free

Re: [coreboot] K8 machine with (a lot of) ram from 2 vendors keeps resetting

ram on CPU1 and all kingston ram on CPU2, as you suggested on irc. Anything else I should try? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] HP dl145 g3

for this? Or is adding a cmdline option considered a good solution? I think that should be considered a bug. Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] unstable AMD Fam10h boot

. This value appears if the result of the cpuid call (or NB probe) is 0xff (the highest 8 bits aren't counted in, it might be 0x, too)' I've seen this occasionally, too. I suspected compiler issues again... Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation

Re: [coreboot] Memtest86

, but it highly depended on the version I tried. I think, maybe, that 3.4 was working for me but I'm not sure. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] Tyan S2912[Fam10] HTX problem

CONFIG_HT_* settings are correct? I found that CONFIG_HT_CHAIN_UNITID_BASE really has to be 1 to get a bootable system with mcp55 on fam10. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

On Thu, Aug 06, 2009 at 10:26:38AM +0800, Bao, Zheng wrote: I am trying to port the ddr3 feature. I will submit a full patch to replace this one. Sounds good, thanks. I won't be able to test until the end of August though, but perhaps someone else can ack before then. Thanks, Ward. -- Ward

[coreboot] seabios head breaking irqs?

-gf.cap OK: http://ward.vandewege.net/coreboot/h8dmr/fam10/h8dmr-gg.cap I'm not sure if this could be caused by seabios, or if perhaps it's yet another toolchain problem. When reverting to the older seabios, the irq problems went away again. Thanks, Ward. -- Ward Vandewege w...@gnu.org

[coreboot] solved - Re: fam10/h8dmr: extreme slowness in CBFS memset /memcpy

noticed that about one in every 10 burn/boot cycles or so, the slowness would not be there. So I switched back to gcc-3.4 (GCC) 3.4.6 (Ubuntu 3.4.6-8ubuntu2) on 32 bit, and it's gone altogether, every time. Is anyone else using gcc 4.3 (32 bit) to compile coreboot? Thanks! Ward. -- Ward

Re: [coreboot] coreboot cbfs incorrect bootblock size

://www.coreboot.org/pipermail/coreboot/2009-June/049363.html where Patrick explained how to convert a board to CBFS. I've used those instructions with success before. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list

Re: [coreboot] fam10/h8dmr: extreme slowness in CBFS memset / memcpy

of these things. Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

on this RB-C2. This patch is just half tested. I am not confident it is 100% correct. Zheng Signed-off-by: Zheng Bao zheng@amd.com With this patch, I can still boot my system with 00100F42h (RB-C2) CPUs - Opteron 2372HE. Acked-by: Ward Vandewege w...@gnu.org Thanks, Ward. -- Ward

Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

/documentation/guides/Pages/default.aspx to the Fam10 revision guide is wrong, the correct link is http://support.amd.com/us/Processor_TechDocs/41322.pdf The actual socket type should be read from CPUID_8001_EBX. Right? I think so, according to the revision guide... Thanks, Ward. -- Ward

Re: [coreboot] fam10/h8dmr: extreme slowness in CBFS memset / memcpy

= 512MB: uncachable, count=1 Any thoughts on something else I should look at to debug this? Thanks, Ward. On Sun, Jul 19, 2009 at 09:23:21PM -0400, Ward Vandewege wrote: Hi all, I'm working on a fam10 tree for supermicro h8dmr. I'm using CBFS. It boots, but I'm struggling with some extreme

[coreboot] fam10/h8dmr: extreme slowness in CBFS memset / memcpy

at the logs it seems MTRRs are not set up until well after CBFS has dealt with coreboot_ram. This box has 32GB of ram, in case that makes a difference. Any suggestions? Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

[coreboot] [PATCH] update AM2 CPU names as per AMD revision guide

See attached... Thanks, Ward. -- Ward Vandewege w...@gnu.org Bring AM2 cpu names up to date with the official Revision Guide for AMD NPT Family 0Fh Processors Rev. 3.42 March 2009, found at http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf This patch takes its

[coreboot] [PATCH] update Socket F CPU names as per AMD revision guide

See attached... Thanks, Ward. -- Ward Vandewege w...@gnu.org Bring Socket F cpu names up to date with the official Revision Guide for AMD NPT Family 0Fh Processors Rev. 3.42 March 2009, found at http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf This patch takes

[coreboot] [PATCH] update S1g1 CPU names as per AMD revision guide

See attached... Thanks, Ward. -- Ward Vandewege w...@gnu.org Bring S1g1 cpu names up to date with the official Revision Guide for AMD NPT Family 0Fh Processors Rev. 3.42 March 2009, found at http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf This patch takes its

Re: [coreboot] [PATCH] update AM2 CPU names as per AMD revision guide

On Fri, Jul 17, 2009 at 05:07:31PM +0200, Stefan Reinauer wrote: Ward Vandewege wrote: See attached... Thanks, Ward. Acked-by: Stefan Reinauer ste...@coresystems.de r4432. Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] [PATCH] update Socket F CPU names as per AMD revision guide

This patch takes its data from Table 7. Build tested. Signed-off-by: Ward Vandewege w...@gnu.org Acked-by: Stefan Reinauer ste...@coresystems.de r4433. Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] [PATCH] update S1g1 CPU names as per AMD revision guide

This patch takes its data from Table 9. Build tested. Signed-off-by: Ward Vandewege w...@gnu.org Acked-by: Stefan Reinauer ste...@coresystems.de r4434. Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo

Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

certainly talking about Socket F. I have a few Opteron 2372 HE CPUs that are 0x100F42. You can contact tim.per...@amd.com about the patch releasing. Thank you, I have done so. Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2

to the list. I am not confident it is 100% correct. I'll test tonight or tomorrow and let you know how it goes. Thanks! Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] add pretty cpu name for Athlon X2 5050e

See attached. I'm not sure if I could predict the IDs for the 4050e/4450e/4850e - anyone know? I only have a 5050e. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator Add pretty name for AMD Athlon(tm) 64 X2 Dual Core Processor 5050e. Boot

Re: [coreboot] What is the way to add a VGA ROM space in target\xx\xx\Config.lb

is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). Leave 36k for VSA. option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024) So, CONFIG_ROM_SIZE is the place to do that. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior

Re: [coreboot] SPI emulator

On Wed, Jul 15, 2009 at 05:07:23PM -0700, ron minnich wrote: any comments on this one? http://microcontrollershop.com/product_info.php?cPath=180products_id=3406 Meh, requires Windows... Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator

Re: [coreboot] m57sli, seabios and gpxe - kernel booting issues (BUG: INT 14 etc)

On Tue, Jul 07, 2009 at 10:51:56PM -0400, Ward Vandewege wrote: On Wed, Jul 08, 2009 at 12:53:02AM +0200, Peter Stuge wrote: Ward Vandewege wrote: I'm trying to do a GPXE boot from seabios with coreboot on m57sli, .. With 2.6.30, I get absolutely nothing, the kernel just hangs

[coreboot] m57sli, seabios and gpxe - kernel booting issues (BUG: INT 14 etc)

, the same kernel boots fine if booted directly from seabios (from disk). In fact, *all* the kernels I tried boot fine from disk. So is GPXE doing something funky here, or is there something else going on? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems

[coreboot] [PATCH] convert h8dmr to CBFS

The patch comment says it all... Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator Convert Supermicro H8DMR to CBFS. Also clean up some whitespace in targets/supermicro/h8dmr/Config.lb and Config-abuild.lb. Importantly, this also sets

Re: [coreboot] [PATCH] Handle programmer init errors, fix IT87* SPI init

the I/O port detected by the IT87* SPI code. Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net Acked-by: Ward Vandewege w...@gnu.org Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot

Re: [coreboot] [RFC] killing the old flashrom tree

, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] locking...

On Sat, Jun 20, 2009 at 02:08:08PM -0400, Ward Vandewege wrote: On Sat, Jun 20, 2009 at 10:13:04AM -0700, ron minnich wrote: That is fine. That's a simple and straightforward change. How about we start with that. But let's not do THAT change until we fix ward's problem, and this has nothing

Re: [coreboot] locking...

per cpu. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [workaround found] locking...

the output in this particular case? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [workaround found] locking...

me to 1 core. Sigh. Patrick, I'm really interested in figuring out why you are seeing none of these problems with the K8 boards you tested 4315 on. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot

Re: [coreboot] [workaround found] locking...

On Wed, Jun 24, 2009 at 03:05:26PM -0400, Ward Vandewege wrote: On Wed, Jun 24, 2009 at 12:51:29PM -0600, Myles Watson wrote: So, I got it to boot by setting CONFIG_AP_CODE_IN_CAR to off. That way the APs don't stumble over one another, and the machine boots just fine. Here's

Re: [coreboot] locking...

;) So, Stepan thinks that perhaps the stack is too small for the lzma decompression. I'm going to test next week with a 32KB stack (right now its at the default 8KB). This might solve booting, but I'll still have APs and BSP talking all at once, which I'm also seeing on K10. Thanks, Ward. -- Ward

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