On 2012-08-27 12:31, Bill Fairchild wrote: > > LA R0,3 > NR R1,R15 > BNZ BAD_RC > > And in 3 or 4 years, IBM will have implemented all of this logic in a single > instruction with an opcode something like this: LANRBNZ. And the processors > will have over 4K different opcodes by then. > The Data General Nova had no condition code in the PSW and no conditional branch. Rather, each RR instruction had a condition mask to cause the next instruction (usually a branch) to be skipped if the result of the operation met thecondition. Plus another bit in each RR instruction to suppress loading of the target register.
-- gil
