That is a RISC-like approach. I have read a bit on the ARM architecture and was impressed by it. It does have a condition code register. And most of the instructions have a "mask" which makes their execution conditional on the CC register, like a branch is conditional on the CC.
-- John McKown Systems Engineer IV IT Administrative Services Group HealthMarkets(r) 9151 Boulevard 26 * N. Richland Hills * TX 76010 (817) 255-3225 phone * john.mck...@healthmarkets.com * www.HealthMarkets.com Confidentiality Notice: This e-mail message may contain confidential or proprietary information. If you are not the intended recipient, please contact the sender by reply e-mail and destroy all copies of the original message. HealthMarkets(r) is the brand name for products underwritten and issued by the insurance subsidiaries of HealthMarkets, Inc. -The Chesapeake Life Insurance Company(r), Mid-West National Life Insurance Company of TennesseeSM and The MEGA Life and Health Insurance Company.SM > -----Original Message----- > From: IBM Mainframe Assembler List [mailto:ASSEMBLER- > l...@listserv.uga.edu] On Behalf Of Paul Gilmartin > Sent: Monday, August 27, 2012 9:54 PM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Re: which instructions should I use? > > On 2012-08-27 12:31, Bill Fairchild wrote: > > > > LA R0,3 > > NR R1,R15 > > BNZ BAD_RC > > > > And in 3 or 4 years, IBM will have implemented all of this logic in a > single instruction with an opcode something like this: LANRBNZ. And > the processors will have over 4K different opcodes by then. > > > The Data General Nova had no condition code in the PSW > and no conditional branch. Rather, each RR instruction > had a condition mask to cause the next instruction > (usually a branch) to be skipped if the result of the > operation met thecondition. Plus another bit in each > RR instruction to suppress loading of the target register. > > -- gil
