Interface jitter on the SPDIF can be accounted for with a PLL to recover a bit perfect digital data stream. The issue is the jitter on the clocking which runs the buffered digital words through the DAC.
NB Why don't we demand to know about the jitter on the ADC used to create the first digital data stream? -- amcluesent ------------------------------------------------------------------------ amcluesent's Profile: http://forums.slimdevices.com/member.php?userid=10286 View this thread: http://forums.slimdevices.com/showthread.php?t=37044 _______________________________________________ audiophiles mailing list audiophiles@lists.slimdevices.com http://lists.slimdevices.com/lists/listinfo/audiophiles
