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commit 47b7b14423f6d96b35712a53089724cf42f2ef68 Author: raiden00pl <[email protected]> AuthorDate: Mon Aug 24 10:10:57 2026 +0200 arch/arm/stm32: Generalize Cortex-M33 USART support Rename the shared U3/U5 USART sources to stm32_serial_m33_v3.c and stm32_lowputc_usart_m33_v3.c and gate them with a new STM32_HAVE_IP_USART_M33_V3 symbol selected by the U3 and U5 peripheral options. Rename the USART hardware header to stm32_uart_m33_v3.h with its register map unchanged. Store each port's RCC enable register and bit in the serial descriptor, provided by the family RCC headers as STM32_<port>_FREQUENCY, _RCC_REG and _RCC_EN, so common clock control needs no family-specific switch. Correct the LPUART1 RX DMA map name to DMAMAP_LPUART1_RX. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/src/common/stm32/CMakeLists.txt | 7 +- arch/arm/src/common/stm32/Kconfig.have | 4 ++ arch/arm/src/common/stm32/Make.defs | 7 +- .../{stm32_uart_m33_u3u5.h => stm32_uart_m33_v3.h} | 8 +-- ...utc_m33_u3u5.c => stm32_lowputc_usart_m33_v3.c} | 32 ++++----- arch/arm/src/common/stm32/stm32_rcc_m33_u5.h | 22 +++++- ...m32_serial_m33_u3u5.c => stm32_serial_m33_v3.c} | 78 +++++++--------------- arch/arm/src/common/stm32/stm32_uart.h | 5 +- .../{stm32_uart_m33_u3u5.h => stm32_uart_m33_v3.h} | 16 ++--- arch/arm/src/stm32u3/Kconfig | 1 + arch/arm/src/stm32u3/stm32_rcc_m33_u3.h | 22 +++++- arch/arm/src/stm32u5/Kconfig | 1 + 12 files changed, 108 insertions(+), 95 deletions(-) diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index 1fa9e9b96e7..780b04b8b31 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -40,8 +40,11 @@ if(NOT CONFIG_ARCH_CUSTOM_PMINIT AND (CONFIG_STM32_COMMON_LEGACY endif() if(CONFIG_ARCH_CHIP_STM32U3 OR CONFIG_ARCH_CHIP_STM32U5) - list(APPEND SRCS stm32_allocateheap_m33_u3u5.c stm32_lowputc_m33_u3u5.c - stm32_serial_m33_u3u5.c stm32_start_m33_u3u5.c) + list(APPEND SRCS stm32_allocateheap_m33_u3u5.c stm32_start_m33_u3u5.c) +endif() + +if(CONFIG_STM32_HAVE_IP_USART_M33_V3) + list(APPEND SRCS stm32_lowputc_usart_m33_v3.c stm32_serial_m33_v3.c) endif() if(CONFIG_STM32_HAVE_IP_GPIO_M33_V1) diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have index 725ee706d27..9f3ab9a9041 100644 --- a/arch/arm/src/common/stm32/Kconfig.have +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -1098,6 +1098,10 @@ config STM32_HAVE_UART8 config STM32_HAVE_IP_USART bool +config STM32_HAVE_IP_USART_M33_V3 + bool + select STM32_HAVE_IP_USART + config STM32_HAVE_IP_USART_V1 bool select STM32_HAVE_IP_USART diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index 8f6296957dc..a6bd35f75fa 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -52,11 +52,14 @@ endif ifneq ($(filter y,$(CONFIG_ARCH_CHIP_STM32U3) \ $(CONFIG_ARCH_CHIP_STM32U5)),) CHIP_CSRCS += stm32_allocateheap_m33_u3u5.c -CHIP_CSRCS += stm32_lowputc_m33_u3u5.c -CHIP_CSRCS += stm32_serial_m33_u3u5.c CHIP_CSRCS += stm32_start_m33_u3u5.c endif +ifeq ($(CONFIG_STM32_HAVE_IP_USART_M33_V3),y) +CHIP_CSRCS += stm32_lowputc_usart_m33_v3.c +CHIP_CSRCS += stm32_serial_m33_v3.c +endif + ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M33_V1),y) CHIP_CSRCS += stm32_gpio_m33_v1.c endif diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart_m33_u3u5.h b/arch/arm/src/common/stm32/hardware/stm32_uart_m33_v3.h similarity index 98% rename from arch/arm/src/common/stm32/hardware/stm32_uart_m33_u3u5.h rename to arch/arm/src/common/stm32/hardware/stm32_uart_m33_v3.h index 5cbb2845f22..6225a68218d 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_uart_m33_u3u5.h +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_m33_v3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/hardware/stm32_uart_m33_u3u5.h + * arch/arm/src/common/stm32/hardware/stm32_uart_m33_v3.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_M33_U3U5_H -#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_M33_U3U5_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_M33_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_M33_V3_H /**************************************************************************** * Included Files @@ -415,4 +415,4 @@ #define USART_AUTOCR_TRIGSEL_MASK (0xf << USART_AUTOCR_TRIGSEL_SHIFT) #define USART_AUTOCR_TRIGSEL(n) ((n) << USART_AUTOCR_TRIGSEL_SHIFT) -#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_M33_U3U5_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_M33_V3_H */ diff --git a/arch/arm/src/common/stm32/stm32_lowputc_m33_u3u5.c b/arch/arm/src/common/stm32/stm32_lowputc_usart_m33_v3.c similarity index 93% rename from arch/arm/src/common/stm32/stm32_lowputc_m33_u3u5.c rename to arch/arm/src/common/stm32/stm32_lowputc_usart_m33_v3.c index f93d5cfa286..b6249c2b1a5 100644 --- a/arch/arm/src/common/stm32/stm32_lowputc_m33_u3u5.c +++ b/arch/arm/src/common/stm32/stm32_lowputc_usart_m33_v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_lowputc_m33_u3u5.c + * arch/arm/src/common/stm32/stm32_lowputc_usart_m33_v3.c * * SPDX-License-Identifier: Apache-2.0 * @@ -66,9 +66,9 @@ # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) # define STM32_CONSOLE_BASE STM32_USART1_BASE -# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR -# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_APBCLOCK STM32_USART1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_USART1_RCC_REG +# define STM32_CONSOLE_APBEN STM32_USART1_RCC_EN # define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD # define STM32_CONSOLE_BITS CONFIG_USART1_BITS # define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY @@ -85,9 +85,9 @@ # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) # define STM32_CONSOLE_BASE STM32_USART2_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 -# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN +# define STM32_APBCLOCK STM32_USART2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_USART2_RCC_REG +# define STM32_CONSOLE_APBEN STM32_USART2_RCC_EN # define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD # define STM32_CONSOLE_BITS CONFIG_USART2_BITS # define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY @@ -104,9 +104,9 @@ # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) # define STM32_CONSOLE_BASE STM32_USART3_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 -# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART3EN +# define STM32_APBCLOCK STM32_USART3_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_USART3_RCC_REG +# define STM32_CONSOLE_APBEN STM32_USART3_RCC_EN # define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD # define STM32_CONSOLE_BITS CONFIG_USART3_BITS # define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY @@ -123,9 +123,9 @@ # endif # elif defined(CONFIG_UART4_SERIAL_CONSOLE) # define STM32_CONSOLE_BASE STM32_UART4_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 -# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART4EN +# define STM32_APBCLOCK STM32_UART4_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_UART4_RCC_REG +# define STM32_CONSOLE_APBEN STM32_UART4_RCC_EN # define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD # define STM32_CONSOLE_BITS CONFIG_UART4_BITS # define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY @@ -142,9 +142,9 @@ # endif # elif defined(CONFIG_UART5_SERIAL_CONSOLE) # define STM32_CONSOLE_BASE STM32_UART5_BASE -# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 -# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART5EN +# define STM32_APBCLOCK STM32_UART5_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_UART5_RCC_REG +# define STM32_CONSOLE_APBEN STM32_UART5_RCC_EN # define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD # define STM32_CONSOLE_BITS CONFIG_UART5_BITS # define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY diff --git a/arch/arm/src/common/stm32/stm32_rcc_m33_u5.h b/arch/arm/src/common/stm32/stm32_rcc_m33_u5.h index 602791ab6ac..e0f69cb2a4e 100644 --- a/arch/arm/src/common/stm32/stm32_rcc_m33_u5.h +++ b/arch/arm/src/common/stm32/stm32_rcc_m33_u5.h @@ -42,12 +42,32 @@ * Pre-processor Definitions ****************************************************************************/ -/* LPUART1 is clocked from PCLK3 by default and is gated through APB3. */ +/* Common Cortex-M33 USART driver contract */ #define STM32_LPUART1_FREQUENCY STM32_PCLK3_FREQUENCY #define STM32_LPUART1_RCC_REG STM32_RCC_APB3ENR #define STM32_LPUART1_RCC_EN RCC_APB3ENR_LPUART1EN +#define STM32_USART1_FREQUENCY STM32_PCLK2_FREQUENCY +#define STM32_USART1_RCC_REG STM32_RCC_APB2ENR +#define STM32_USART1_RCC_EN RCC_APB2ENR_USART1EN + +#define STM32_USART2_FREQUENCY STM32_PCLK1_FREQUENCY +#define STM32_USART2_RCC_REG STM32_RCC_APB1ENR1 +#define STM32_USART2_RCC_EN RCC_APB1ENR1_USART2EN + +#define STM32_USART3_FREQUENCY STM32_PCLK1_FREQUENCY +#define STM32_USART3_RCC_REG STM32_RCC_APB1ENR1 +#define STM32_USART3_RCC_EN RCC_APB1ENR1_USART3EN + +#define STM32_UART4_FREQUENCY STM32_PCLK1_FREQUENCY +#define STM32_UART4_RCC_REG STM32_RCC_APB1ENR1 +#define STM32_UART4_RCC_EN RCC_APB1ENR1_UART4EN + +#define STM32_UART5_FREQUENCY STM32_PCLK1_FREQUENCY +#define STM32_UART5_RCC_REG STM32_RCC_APB1ENR1 +#define STM32_UART5_RCC_EN RCC_APB1ENR1_UART5EN + #ifndef __ASSEMBLY__ #undef EXTERN diff --git a/arch/arm/src/common/stm32/stm32_serial_m33_u3u5.c b/arch/arm/src/common/stm32/stm32_serial_m33_v3.c similarity index 98% rename from arch/arm/src/common/stm32/stm32_serial_m33_u3u5.c rename to arch/arm/src/common/stm32/stm32_serial_m33_v3.c index 88e93d77c06..301e9306b60 100644 --- a/arch/arm/src/common/stm32/stm32_serial_m33_u3u5.c +++ b/arch/arm/src/common/stm32/stm32_serial_m33_v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_serial_m33_u3u5.c + * arch/arm/src/common/stm32/stm32_serial_m33_v3.c * * SPDX-License-Identifier: Apache-2.0 * @@ -261,6 +261,8 @@ struct stm32_serial_s const uint8_t irq; /* IRQ associated with this USART */ const uint32_t apbclock; /* PCLK 1 or 2 frequency */ + const uint32_t rccreg; /* RCC enable register */ + const uint32_t rccen; /* RCC enable bit */ const uint32_t usartbase; /* Base address of USART registers */ const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */ const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ @@ -478,6 +480,8 @@ static struct stm32_serial_s g_lpuart1priv = .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, .apbclock = STM32_LPUART1_FREQUENCY, + .rccreg = STM32_LPUART1_RCC_REG, + .rccen = STM32_LPUART1_RCC_EN, .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, @@ -490,7 +494,7 @@ static struct stm32_serial_s g_lpuart1priv = .rts_gpio = GPIO_LPUART1_RTS, # endif # ifdef CONFIG_LPUART1_RXDMA - .rxdma_channel = DMAMAP_LPUSART_RX, + .rxdma_channel = DMAMAP_LPUART1_RX, .rxfifo = g_lpuart1rxfifo, # endif @@ -537,7 +541,9 @@ static struct stm32_serial_s g_usart1priv = .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32_PCLK2_FREQUENCY, + .apbclock = STM32_USART1_FREQUENCY, + .rccreg = STM32_USART1_RCC_REG, + .rccen = STM32_USART1_RCC_EN, .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, @@ -599,7 +605,9 @@ static struct stm32_serial_s g_usart2priv = .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, + .apbclock = STM32_USART2_FREQUENCY, + .rccreg = STM32_USART2_RCC_REG, + .rccen = STM32_USART2_RCC_EN, .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, @@ -661,7 +669,9 @@ static struct stm32_serial_s g_usart3priv = .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, .baud = CONFIG_USART3_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, + .apbclock = STM32_USART3_FREQUENCY, + .rccreg = STM32_USART3_RCC_REG, + .rccen = STM32_USART3_RCC_EN, .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, @@ -731,7 +741,9 @@ static struct stm32_serial_s g_uart4priv = .rts_gpio = GPIO_UART4_RTS, # endif .baud = CONFIG_UART4_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, + .apbclock = STM32_UART4_FREQUENCY, + .rccreg = STM32_UART4_RCC_REG, + .rccen = STM32_UART4_RCC_EN, .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, @@ -793,7 +805,9 @@ static struct stm32_serial_s g_uart5priv = .rts_gpio = GPIO_UART5_RTS, # endif .baud = CONFIG_UART5_BAUD, - .apbclock = STM32_PCLK1_FREQUENCY, + .apbclock = STM32_UART5_FREQUENCY, + .rccreg = STM32_UART5_RCC_REG, + .rccen = STM32_UART5_RCC_EN, .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, @@ -1323,62 +1337,16 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) { struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - uint32_t rcc_en; - uint32_t regaddr; - - /* Determine which USART to configure */ - - switch (priv->usartbase) - { - default: - return; -#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER - case STM32_LPUART1_BASE: - rcc_en = STM32_LPUART1_RCC_EN; - regaddr = STM32_LPUART1_RCC_REG; - break; -#endif -#ifdef CONFIG_STM32_USART1_SERIALDRIVER - case STM32_USART1_BASE: - rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32_RCC_APB2ENR; - break; -#endif -#ifdef CONFIG_STM32_USART2_SERIALDRIVER - case STM32_USART2_BASE: - rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32_RCC_APB1ENR1; - break; -#endif -#ifdef CONFIG_STM32_USART3_SERIALDRIVER - case STM32_USART3_BASE: - rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32_RCC_APB1ENR1; - break; -#endif -#ifdef CONFIG_STM32_UART4_SERIALDRIVER - case STM32_UART4_BASE: - rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32_RCC_APB1ENR1; - break; -#endif -#ifdef CONFIG_STM32_UART5_SERIALDRIVER - case STM32_UART5_BASE: - rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32_RCC_APB1ENR1; - break; -#endif - } /* Enable/disable APB 1/2 clock for USART */ if (on) { - modifyreg32(regaddr, 0, rcc_en); + modifyreg32(priv->rccreg, 0, priv->rccen); } else { - modifyreg32(regaddr, rcc_en, 0); + modifyreg32(priv->rccreg, priv->rccen, 0); } } diff --git a/arch/arm/src/common/stm32/stm32_uart.h b/arch/arm/src/common/stm32/stm32_uart.h index 439b856885b..fb3cfc87e54 100644 --- a/arch/arm/src/common/stm32/stm32_uart.h +++ b/arch/arm/src/common/stm32/stm32_uart.h @@ -27,9 +27,8 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_ARCH_CHIP_STM32U3) || \ - defined(CONFIG_ARCH_CHIP_STM32U5) -# include "stm32_uart_m33_u3u5.h" +#if defined(CONFIG_STM32_HAVE_IP_USART_M33_V3) +# include "stm32_uart_m33_v3.h" #elif defined(CONFIG_ARCH_ARMV6M) # if defined(CONFIG_STM32_HAVE_IP_USART_V3) || \ defined(CONFIG_STM32_HAVE_IP_USART_V4) diff --git a/arch/arm/src/common/stm32/stm32_uart_m33_u3u5.h b/arch/arm/src/common/stm32/stm32_uart_m33_v3.h similarity index 95% rename from arch/arm/src/common/stm32/stm32_uart_m33_u3u5.h rename to arch/arm/src/common/stm32/stm32_uart_m33_v3.h index 9af52e8a968..f9a0d136848 100644 --- a/arch/arm/src/common/stm32/stm32_uart_m33_u3u5.h +++ b/arch/arm/src/common/stm32/stm32_uart_m33_v3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_uart_m33_u3u5.h + * arch/arm/src/common/stm32/stm32_uart_m33_v3.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M33_U3U5_H -#define __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M33_U3U5_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M33_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M33_V3_H /**************************************************************************** * Included Files @@ -32,13 +32,7 @@ #include "chip.h" -#if defined(CONFIG_STM32_STM32U3C5XX) || \ - defined(CONFIG_STM32_STM32U585XX) || \ - defined(CONFIG_STM32_STM32U5A5XX) -# include "hardware/stm32_uart_m33_u3u5.h" -#else -# error "Unsupported STM32U3/U5 chip" -#endif +#include "hardware/stm32_uart_m33_v3.h" /**************************************************************************** * Pre-processor Definitions @@ -299,4 +293,4 @@ void stm32_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M33_U3U5_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M33_V3_H */ diff --git a/arch/arm/src/stm32u3/Kconfig b/arch/arm/src/stm32u3/Kconfig index 824f50e0c46..20ce6236ef5 100644 --- a/arch/arm/src/stm32u3/Kconfig +++ b/arch/arm/src/stm32u3/Kconfig @@ -12,6 +12,7 @@ config STM32_U3_PERIPHERALS default y select STM32_HAVE_IP_EXTI_M33_V1 select STM32_HAVE_IP_GPIO_M33_V1 + select STM32_HAVE_IP_USART_M33_V3 select STM32_HAVE_SYSCFG select STM32_HAVE_USART1 select STM32_HAVE_USART2 diff --git a/arch/arm/src/stm32u3/stm32_rcc_m33_u3.h b/arch/arm/src/stm32u3/stm32_rcc_m33_u3.h index 2e0560d2ee3..d0285e4e85f 100644 --- a/arch/arm/src/stm32u3/stm32_rcc_m33_u3.h +++ b/arch/arm/src/stm32u3/stm32_rcc_m33_u3.h @@ -35,12 +35,32 @@ * Pre-processor Definitions ****************************************************************************/ -/* LPUART1 is clocked from PCLK3 by default and is gated through APB3. */ +/* Common Cortex-M33 USART driver contract */ #define STM32_LPUART1_FREQUENCY STM32_PCLK3_FREQUENCY #define STM32_LPUART1_RCC_REG STM32_RCC_APB3ENR #define STM32_LPUART1_RCC_EN RCC_APB3ENR_LPUART1EN +#define STM32_USART1_FREQUENCY STM32_PCLK2_FREQUENCY +#define STM32_USART1_RCC_REG STM32_RCC_APB2ENR +#define STM32_USART1_RCC_EN RCC_APB2ENR_USART1EN + +#define STM32_USART2_FREQUENCY STM32_PCLK1_FREQUENCY +#define STM32_USART2_RCC_REG STM32_RCC_APB1ENR1 +#define STM32_USART2_RCC_EN RCC_APB1ENR1_USART2EN + +#define STM32_USART3_FREQUENCY STM32_PCLK1_FREQUENCY +#define STM32_USART3_RCC_REG STM32_RCC_APB1ENR1 +#define STM32_USART3_RCC_EN RCC_APB1ENR1_USART3EN + +#define STM32_UART4_FREQUENCY STM32_PCLK1_FREQUENCY +#define STM32_UART4_RCC_REG STM32_RCC_APB1ENR1 +#define STM32_UART4_RCC_EN RCC_APB1ENR1_UART4EN + +#define STM32_UART5_FREQUENCY STM32_PCLK1_FREQUENCY +#define STM32_UART5_RCC_REG STM32_RCC_APB1ENR1 +#define STM32_UART5_RCC_EN RCC_APB1ENR1_UART5EN + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index 005ea2162f6..7e8198aaa13 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -12,6 +12,7 @@ config STM32_U5_PERIPHERALS default y select STM32_HAVE_IP_EXTI_M33_V1 select STM32_HAVE_IP_GPIO_M33_V1 + select STM32_HAVE_IP_USART_M33_V3 select STM32_HAVE_COMP select STM32_HAVE_CRS select STM32_HAVE_DAC1
