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commit b269bb0c914e018e3aa750f79c73be53414a4cc7 Author: raiden00pl <[email protected]> AuthorDate: Mon Aug 24 10:13:56 2026 +0200 arch/arm/stm32: Generalize Cortex-M33 startup Rename the shared U3/U5 reset handler to stm32_start_m33_v1.c and keep its direct family selection in Make and CMake. Include stm32_userspace.h only under CONFIG_BUILD_PROTECTED and define the SRAM2 span only when CONFIG_STM32_SRAM2_INIT requests the parity initialization, so families without SRAM2 parity or userspace support can use the file unchanged. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/src/common/stm32/CMakeLists.txt | 5 +++-- arch/arm/src/common/stm32/Make.defs | 2 +- .../{stm32_start_m33_u3u5.c => stm32_start_m33_v1.c} | 18 +++++++++++------- 3 files changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index 780b04b8b31..463ec4cdc14 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -40,7 +40,7 @@ if(NOT CONFIG_ARCH_CUSTOM_PMINIT AND (CONFIG_STM32_COMMON_LEGACY endif() if(CONFIG_ARCH_CHIP_STM32U3 OR CONFIG_ARCH_CHIP_STM32U5) - list(APPEND SRCS stm32_allocateheap_m33_u3u5.c stm32_start_m33_u3u5.c) + list(APPEND SRCS stm32_allocateheap_m33_u3u5.c) endif() if(CONFIG_STM32_HAVE_IP_USART_M33_V3) @@ -56,7 +56,8 @@ if(CONFIG_STM32_HAVE_IP_EXTI_M33_V1) endif() if(CONFIG_ARCH_CHIP_STM32U3 OR CONFIG_ARCH_CHIP_STM32U5) - list(APPEND SRCS stm32_irq_m33_v1.c stm32_timerisr_m33_v1.c) + list(APPEND SRCS stm32_irq_m33_v1.c stm32_start_m33_v1.c + stm32_timerisr_m33_v1.c) if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle_m33_v1.c) diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index a6bd35f75fa..8b9563891ee 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -52,7 +52,6 @@ endif ifneq ($(filter y,$(CONFIG_ARCH_CHIP_STM32U3) \ $(CONFIG_ARCH_CHIP_STM32U5)),) CHIP_CSRCS += stm32_allocateheap_m33_u3u5.c -CHIP_CSRCS += stm32_start_m33_u3u5.c endif ifeq ($(CONFIG_STM32_HAVE_IP_USART_M33_V3),y) @@ -71,6 +70,7 @@ endif ifneq ($(filter y,$(CONFIG_ARCH_CHIP_STM32U3) \ $(CONFIG_ARCH_CHIP_STM32U5)),) CHIP_CSRCS += stm32_irq_m33_v1.c +CHIP_CSRCS += stm32_start_m33_v1.c CHIP_CSRCS += stm32_timerisr_m33_v1.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle_m33_v1.c diff --git a/arch/arm/src/common/stm32/stm32_start_m33_u3u5.c b/arch/arm/src/common/stm32/stm32_start_m33_v1.c similarity index 94% rename from arch/arm/src/common/stm32/stm32_start_m33_u3u5.c rename to arch/arm/src/common/stm32/stm32_start_m33_v1.c index b5df8e2d67c..26e0a8d43ec 100644 --- a/arch/arm/src/common/stm32/stm32_start_m33_u3u5.c +++ b/arch/arm/src/common/stm32/stm32_start_m33_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_start_m33_u3u5.c + * arch/arm/src/common/stm32/stm32_start_m33_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -38,9 +38,12 @@ #include "stm32.h" #include "stm32_gpio.h" -#include "stm32_userspace.h" #include "stm32_start.h" +#ifdef CONFIG_BUILD_PROTECTED +# include "stm32_userspace.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -48,13 +51,14 @@ /* Memory map ***************************************************************/ /* Internal flash begins at STM32_FLASH_BASE and contains the vector table. - * SRAM1 begins at STM32_SRAM1_BASE and contains .data, .bss, the idle stack, - * and the primary heap. SRAM2 locations and sizes vary between the STM32U3 - * and STM32U5 families and are provided by the chip header. + * The primary SRAM contains .data, .bss, the idle stack and the primary + * heap. A family may also request parity initialization of SRAM2. */ -#define SRAM2_START STM32_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) +#ifdef CONFIG_STM32_SRAM2_INIT +# define SRAM2_START STM32_SRAM2_BASE +# define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) +#endif #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE)
