This is an automated email from the ASF dual-hosted git repository. xiaoxiang781216 pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit e20c4a76b6ae92c2c9ab0ec8361c554e58a31122 Author: raiden00pl <[email protected]> AuthorDate: Mon Aug 24 11:33:18 2026 +0200 arch/arm/stm32: Generalize Cortex-M33 heap support Rename the shared U3/U5 heap allocator to stm32_allocateheap_m33_v1.c and keep its direct family selection in Make and CMake. Size the primary region from a now-mandatory STM32_PRIMARY_SRAM_SIZE, provided by the U5 chip header as the SRAM1 size, and drop the U5-specific SRAM bank descriptions so the allocator carries no family conditionals. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/include/stm32u5/chip.h | 2 ++ arch/arm/src/common/stm32/CMakeLists.txt | 8 ++--- arch/arm/src/common/stm32/Make.defs | 6 +--- ...heap_m33_u3u5.c => stm32_allocateheap_m33_v1.c} | 40 ++++++---------------- 4 files changed, 15 insertions(+), 41 deletions(-) diff --git a/arch/arm/include/stm32u5/chip.h b/arch/arm/include/stm32u5/chip.h index c984c6f80c8..c30d2dac4a7 100644 --- a/arch/arm/include/stm32u5/chip.h +++ b/arch/arm/include/stm32u5/chip.h @@ -49,6 +49,8 @@ # error "Unsupported STM32U5 chip" #endif +#define STM32_PRIMARY_SRAM_SIZE STM32_SRAM1_SIZE + #if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # define STM32_NFSMC 1 /* Have FSMC memory controller */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index 463ec4cdc14..4b1eb9bbb03 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -39,10 +39,6 @@ if(NOT CONFIG_ARCH_CUSTOM_PMINIT AND (CONFIG_STM32_COMMON_LEGACY list(APPEND SRCS stm32_pminitialize_default.c) endif() -if(CONFIG_ARCH_CHIP_STM32U3 OR CONFIG_ARCH_CHIP_STM32U5) - list(APPEND SRCS stm32_allocateheap_m33_u3u5.c) -endif() - if(CONFIG_STM32_HAVE_IP_USART_M33_V3) list(APPEND SRCS stm32_lowputc_usart_m33_v3.c stm32_serial_m33_v3.c) endif() @@ -56,8 +52,8 @@ if(CONFIG_STM32_HAVE_IP_EXTI_M33_V1) endif() if(CONFIG_ARCH_CHIP_STM32U3 OR CONFIG_ARCH_CHIP_STM32U5) - list(APPEND SRCS stm32_irq_m33_v1.c stm32_start_m33_v1.c - stm32_timerisr_m33_v1.c) + list(APPEND SRCS stm32_allocateheap_m33_v1.c stm32_irq_m33_v1.c + stm32_start_m33_v1.c stm32_timerisr_m33_v1.c) if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle_m33_v1.c) diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index 8b9563891ee..e018677a673 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -49,11 +49,6 @@ CHIP_CSRCS += stm32_pminitialize_default.c endif endif -ifneq ($(filter y,$(CONFIG_ARCH_CHIP_STM32U3) \ - $(CONFIG_ARCH_CHIP_STM32U5)),) -CHIP_CSRCS += stm32_allocateheap_m33_u3u5.c -endif - ifeq ($(CONFIG_STM32_HAVE_IP_USART_M33_V3),y) CHIP_CSRCS += stm32_lowputc_usart_m33_v3.c CHIP_CSRCS += stm32_serial_m33_v3.c @@ -69,6 +64,7 @@ endif ifneq ($(filter y,$(CONFIG_ARCH_CHIP_STM32U3) \ $(CONFIG_ARCH_CHIP_STM32U5)),) +CHIP_CSRCS += stm32_allocateheap_m33_v1.c CHIP_CSRCS += stm32_irq_m33_v1.c CHIP_CSRCS += stm32_start_m33_v1.c CHIP_CSRCS += stm32_timerisr_m33_v1.c diff --git a/arch/arm/src/common/stm32/stm32_allocateheap_m33_u3u5.c b/arch/arm/src/common/stm32/stm32_allocateheap_m33_v1.c similarity index 90% rename from arch/arm/src/common/stm32/stm32_allocateheap_m33_u3u5.c rename to arch/arm/src/common/stm32/stm32_allocateheap_m33_v1.c index 42f0d54f8fb..6e683fd2c3d 100644 --- a/arch/arm/src/common/stm32/stm32_allocateheap_m33_u3u5.c +++ b/arch/arm/src/common/stm32/stm32_allocateheap_m33_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_allocateheap_m33_u3u5.c + * arch/arm/src/common/stm32/stm32_allocateheap_m33_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -47,14 +47,17 @@ * Pre-processor Definitions ****************************************************************************/ -/* Internal SRAM is available in all members of the STM32U3 and STM32U5 - * families. The following definitions specify its family-specific size - * and location: +/* Each family using this implementation provides the following SRAM + * description: * * SRAM1_START STM32_SRAM1_BASE - * SRAM1_END + * SRAM1_END STM32_SRAM1_BASE + STM32_PRIMARY_SRAM_SIZE * SRAM2_START STM32_SRAM2_BASE - * SRAM2_END + * SRAM2_END STM32_SRAM2_BASE + STM32_SRAM2_SIZE + * + * STM32_PRIMARY_SRAM_SIZE may span multiple contiguous SRAM banks. SRAM3 + * and SRAM5 may be added as separate regions when their corresponding heap + * options are selected. * * In addition to internal SRAM, memory may also be available through the * FSMC. In order to use FSMC SRAM, the following additional things need to @@ -75,33 +78,10 @@ # undef CONFIG_STM32_FSMC_SRAM #endif -/* STM32U5[7,8]6xx have 128 KiB in two banks, both accessible to DMA: - * - * 1) 96 KiB of System SRAM beginning at address 0x2000:0000 - 0x2001:8000 - * 2) 32 KiB of System SRAM beginning at address 0x1000:0000 - 0x1000:8000 - * - * STM32U596xx have 320 KiB in two banks, both accessible to DMA: - * - * 1) 256 KiB of System SRAM beginning at address 0x2000:0000 - 0x2004:0000 - * 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000 - * - * STM32U5Rxxx have 640 KiB in three banks: - * - * 1) 192 KiB of System SRAM beginning at address 0x2000:0000 - 0x2003:0000 - * 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000 - * 3) 384 KiB of System SRAM beginning at address 0x2004:0000 - 0x200A:0000 - * - * In addition, external FSMC SRAM may be available. - */ - /* Set the range of system SRAM */ #define SRAM1_START STM32_SRAM1_BASE -#ifdef STM32_PRIMARY_SRAM_SIZE -# define SRAM1_END (SRAM1_START + STM32_PRIMARY_SRAM_SIZE) -#else -# define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) -#endif +#define SRAM1_END (SRAM1_START + STM32_PRIMARY_SRAM_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */
