FranklandJack commented on code in PR #14981:
URL: https://github.com/apache/tvm/pull/14981#discussion_r1213425076
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python/tvm/topi/arm_cpu/conv2d.py:
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@@ -509,3 +510,24 @@ def conv2d_nhwc_dsp(cfg, data, kernel, strides, padding,
dilation, out_dtype):
def schedule_conv2d_nhwc_dsp(cfg, outs):
"""Create schedule for conv2d_nhwc_dsp"""
return conv2d_nhwc_dsp_schedule(cfg, outs)
+
+
+@conv2d_infer_layout.register("arm_cpu")
+def _conv2d_infer_layout(workload, cfg):
+ _, data, kernel, strides, padding, dilation, layout, _, dtype = workload
+ batch_size, in_channel, in_height, in_width = data[1]
+ out_channel, _, k_height, k_width = kernel[1]
+ idxdiv = tvm.tir.indexdiv
+
+ pt, pl, pb, pr = get_pad_tuple(padding, (k_height, k_width))
+ hdilation, wdilation = dilation if isinstance(dilation, (tuple, list))
else (dilation, dilation)
+ dilated_kernel_h = (k_height - 1) * hdilation + 1
+ dilated_kernel_w = (k_width - 1) * wdilation + 1
+ out_height = idxdiv(in_height + pt + pb - dilated_kernel_h, strides[0]) + 1
+ out_width = idxdiv(in_width + pl + pr - dilated_kernel_w, strides[1]) + 1
+ tile_ic, tile_oc = cfg["tile_ic"].size[-1], cfg["tile_oc"].size[-1]
+ in_shape = (batch_size, idxdiv(in_channel, tile_ic), in_height, in_width,
tile_ic)
+ in_layout = f"NCHW{tile_ic}c"
+ out_shape = (batch_size, idxdiv(out_channel, tile_oc), out_height,
out_width, tile_oc)
+ out_layout = f"NCHW{tile_oc}c"
+ return ((in_shape, in_layout),), ((out_shape, out_layout),)
Review Comment:
Yep it was copied directly from there. I guess this will only work for
scheduling definitions that include 'tile_ic' and 'tile_oc' parameters (which
is true for x86, intel_graphics and arm_cpu) but maybe not others? Is that
okay? I guess we can document that.
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