I attached a patch that fixes the problem. It introduces a new
TCL_FALLBACK if there are too many vertices to fit into one DMA buffer.
Looks kind of hackish to me. Does anyone have a better idea? Comments?
Regards,
Felix
On Wed, 5 Feb 2003 12:04:45 +0100
Felix Kühling <[EMAIL PROTECTED]> wrote:
> Hi,
>
> while I was trying to understand the DMA buffer allocation of the radeon
> driver a few months ago I added an assertion at the end of
> radeonAllocDmaRegion:
>
> assert (rmesa->dma.current.ptr <= rmesa->dma.current.end);
>
> It fails if someone tries to allocate more DMA buffer space than one DMA
> buffer size. Now while testing quakeforge after a long time again the
> assertion did actually fail. RADEON_DEBUG=ioctl shows that
> radeonAllocDmaRegion is called with bytes=72000. IIRC the DMA buffer
> size is 65536. Here is a backtrace:
>
> nq-glx: radeon_ioctl.c:635: radeonAllocDmaRegion: Assertion `rmesa->dma.current.ptr
><= rmesa->dma.current.end' failed.
>
> Program received signal SIGABRT, Aborted.
> [Switching to Thread 1024 (LWP 1016)]
> 0x40334581 in kill () from /lib/libc.so.6
> (gdb) bt
> #0 0x40334581 in kill () from /lib/libc.so.6
> #1 0x40334394 in raise () from /lib/libc.so.6
> #2 0x403358d1 in abort () from /lib/libc.so.6
> #3 0x4032edb2 in __assert_fail () from /lib/libc.so.6
> #4 0x41654ce7 in radeonAllocDmaRegion () at radeon_ioctl.c:609
> #5 0x41656442 in radeonEmitArrays (ctx=0x8167898, inputs=24)
> at radeon_maos_verts.c:305
> #6 0x416788e5 in radeon_run_tcl_render (ctx=0x8167898, stage=0x82e2d38)
> at radeon_tcl.c:315
> #7 0x4162f733 in _tnl_run_pipeline (ctx=0x8167898) at t_pipeline.c:154
> #8 0x41661d87 in radeonWrapRunPipeline (ctx=0x8167898) at radeon_state.c:2088
> #9 0x41620115 in _tnl_DrawElements (mode=2823, count=137243856,
> type=137243856, indices=0x8318ba8) at t_array_api.c:99
> #10 0x415bb936 in neutral_DrawElements (mode=0, count=0, type=0, indices=0x0)
> at ../../../../extras/Mesa/src/vtxfmt_tmp.h:369
> #11 0x41680571 in radeon_fallback_DrawElements (mode=0, count=0, type=0,
> indices=0x0) at ../../../../../../extras/Mesa/src/vtxfmt_tmp.h:369
> #12 0x415bb936 in neutral_DrawElements (mode=0, count=0, type=0, indices=0x0)
> at ../../../../extras/Mesa/src/vtxfmt_tmp.h:369
> #13 0x40026f38 in Draw_nString (x=6, y=1078070736,
> str=0x4144e780 "_histogram GL_EXT_packed_pixels GL_EXT_polygon_offset", ' '
><repeats 19 times>, "GL_EXT_rescale_normal GL_EXT_secondary_color GL_EXT_texture3D",
>' ' <repeats 17 times>, "GL_EXT_texture_env_add GL_EXT_texture_env_combine ---Type
><return> to continue, or q <return> to quit---
> "..., count=0) at gl_draw.c:367
> #14 0x72676f74 in ?? ()
> Cannot access memory at address 0x7369685f
__\|/__ ___ ___ ___
__Tschüß_______\_6 6_/___/__ \___/__ \___/___\___You can do anything,___
_____Felix_______\Ä/\ \_____\ \_____\ \______U___just not everything____
[EMAIL PROTECTED] >o<__/ \___/ \___/ at the same time!
Index: radeon_tcl.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_tcl.c,v
retrieving revision 1.5
diff -u -r1.5 radeon_tcl.c
--- radeon_tcl.c 25 Nov 2002 19:58:29 -0000 1.5
+++ radeon_tcl.c 5 Feb 2003 22:15:18 -0000
@@ -303,6 +303,9 @@
struct vertex_buffer *VB = &tnl->vb;
GLuint i,flags = 0,length;
+ /* reset vb count fallback, is this the right place? */
+ TCL_FALLBACK(ctx, RADEON_TCL_FALLBACK_VB_COUNT, GL_FALSE);
+
/* TODO: separate this from the swtnl pipeline
*/
if (rmesa->TclFallback)
@@ -313,6 +316,10 @@
radeonReleaseArrays( ctx, stage->changed_inputs );
radeonEmitArrays( ctx, stage->inputs );
+ /* have to fall back to sw t&l if radeonEmitArrays finds that the vertices
+ * don't fit into one DMA buffer */
+ if (rmesa->TclFallback)
+ return GL_TRUE;
rmesa->tcl.Elts = VB->Elts;
@@ -504,7 +511,8 @@
"Texgen unit 0",
"Texgen unit 1",
"Texgen unit 2",
- "User disable"
+ "User disable",
+ "Too many vertices"
};
Index: radeon_tcl.h
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_tcl.h,v
retrieving revision 1.2
diff -u -r1.2 radeon_tcl.h
--- radeon_tcl.h 12 Jun 2002 15:50:26 -0000 1.2
+++ radeon_tcl.h 5 Feb 2003 22:15:18 -0000
@@ -56,6 +56,7 @@
#define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */
#define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */
#define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */
+#define RADEON_TCL_FALLBACK_VB_COUNT 0x100 /* too many vertices */
#define RADEON_MAX_TCL_VERTSIZE (4*4) /* using maos now... */
Index: radeon_maos_verts.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_maos_verts.c,v
retrieving revision 1.5
diff -u -r1.5 radeon_maos_verts.c
--- radeon_maos_verts.c 25 Nov 2002 19:58:27 -0000 1.5
+++ radeon_maos_verts.c 5 Feb 2003 22:15:19 -0000
@@ -302,6 +302,12 @@
if (rmesa->tcl.indexed_verts.buf)
radeonReleaseArrays( ctx, ~0 );
+ /* vertices must fit into one dma buffer
+ * fall back to software t&l if too many */
+ if (VB->Count * setup_tab[i].vertex_size*4 > RADEON_BUFFER_SIZE) {
+ TCL_FALLBACK(ctx, RADEON_TCL_FALLBACK_VB_COUNT, GL_TRUE);
+ return;
+ }
radeonAllocDmaRegionVerts( rmesa,
&rmesa->tcl.indexed_verts,
VB->Count,
