On Tue, Jan 19, 2010 at 05:29:49PM -0800, Peter C. Wallace wrote: > Being unable to reconfig the FPGA usually means that the FPGA is driving some > line that messes up the bridge (for example hold-holda or /ready are a couple > of fatal pins if driven wrong). When I have that problem, it usually that the > .ucf (constraint) file was not used for some reason. In this case the bitfile > has its pinout assigned willy-nilly. The pad report can be used to verify > that > the generated pinout matches the constraints.
I spot checked a few, including HOLD, HOLDA and READY and they're all in the location specified in 7i68.ucf. Is that the proper constraint file to use for 3x20? Does the 3x20 require non-default bitgen options (-g DONE_cycle and so on) like 7i43? I tried adding these (with the same settings I used on 7i43, for want of a better guess) in a firmware I sent privately to seb, but he hasn't been able to test it yet, and this really is just a stab in the dark, or more like hoping the next problem is the same as the previous one. Jeff ------------------------------------------------------------------------------ Throughout its 18-year history, RSA Conference consistently attracts the world's best and brightest in the field, creating opportunities for Conference attendees to learn about information security's most important issues through interactions with peers, luminaries and emerging and established companies. http://p.sf.net/sfu/rsaconf-dev2dev _______________________________________________ Emc-developers mailing list Emc-developers@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-developers
