>
> No, unlike the 7I43, the 3X20 doesnt care about config options so this is
> fairly mysterious. If you point me to the bad bitfile I'll give it a try here
> and do some probing about.
Well, turns out thats not quite true, the 3X20 doesnt care about DONE but it
DOES care about the order of "Release_Write_Enable" and "Enable_Output"
On the bitfiles that fail, configuration hangs because /READY ends up being
stuck de-asserted by the FPGA before the FPGA is fully configured.
"Release_Write_enable" must come before "Enable Outputs"
Probably best order for 3X20 is
4 Release_Write_enable
5 Enable_Outputs
6 Assert Done
Asserting DONE last wont affect host configuration but is needed for local
EEPROM configuration (it stops config so must be last)
Another solution to this startup timing pickyness would be for the downloader
to disable /READY until the FPGA is configured...
Peter Wallace
Mesa Electronics
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