Peter, Good point about interrupt jitter mattering less if the actual sample time does not jitter. Unfortunately the current RTAI setup requires that the interrupt comes from the host interrupt timers. If we could get to a system model where the hardware could sample the data at the same time that it also requests an interrupt, then the actual interrupt latency would be much less critical. The PC system design does not bring out the interrupt request anywhere, so syncing with it in hardware is not possible, nor can RTAI (as best I know) accept an interrupt from external hardware as the system timer.
I wonder if Preempt-RT may be more flexible. Steve Stallings (unrepentant top poster) -----Original Message----- From: Peter C. Wallace [mailto:[email protected]] Sent: Thursday, July 21, 2011 9:34 AM To: EMC developers Subject: Re: [Emc-developers] Preempt-RT ... where to put the patches ? On Wed, 20 Jul 2011, Jon Elson wrote: > Date: Wed, 20 Jul 2011 20:41:44 -0500 > From: Jon Elson <[email protected]> > Reply-To: EMC developers <[email protected]> > To: EMC developers <[email protected]> > Subject: Re: [Emc-developers] Preempt-RT ... where to put the patches ? > > Viesturs Lcis wrote: > Out of curiosity I tried to find results for D510 and D525 boards - > they both are mentioned in the list of tested systems. > > This is D510: > https://www.osadl.org/Latency-plot-of-system-in-rack-1-slot.qa-latencyplot-r 1s4.0.html?latencies=&showno=&slider=228 > > This is D525: > https://www.osadl.org/Latency-plot-of-system-in-rack-4-slot.qa-latencyplot-r 4s7.0.html?latencies=&showno=&slider=228 > > > Where did they get 4 cores? From hyperthreading? Do I understand > correctly that disabling hyperthreading should improve latency > figures? >Yup, the D510 is a CATASTROPHE, the D525 is just really bad. You could >probably run a servo machine Well 100 uSec of jitter should be perfectly acceptable _if_ the PID (or hardware stepgen) corrections were based on actual time instead of thread invocation time, heck even 500 uSec jitter might be OK. >on the D525, but it isn't real good. Yes, I think the extra "CPUs" are >from hyperthreading, and disabling >it should help. > >Jon ---------------------------------------------------------------------------- -- 5 Ways to Improve & Secure Unified Communications Unified Communications promises greater efficiencies for business. UC can improve internal communications as well as offer faster, more efficient ways to interact with customers and streamline customer service. Learn more! http://www.accelacomm.com/jaw/sfnl/114/51426253/ _______________________________________________ Emc-developers mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-developers Peter Wallace Mesa Electronics (\__/) (='.'=) This is Bunny. Copy and paste bunny into your (")_(") signature to help him gain world domination. ------------------------------------------------------------------------------ 5 Ways to Improve & Secure Unified Communications Unified Communications promises greater efficiencies for business. UC can improve internal communications as well as offer faster, more efficient ways to interact with customers and streamline customer service. Learn more! http://www.accelacomm.com/jaw/sfnl/114/51426253/ _______________________________________________ Emc-developers mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-developers
