On 7/21/2011 11:53 AM, Peter C. Wallace wrote:
> On Thu, 21 Jul 2011, Steve Stallings wrote:
>
>    
>> Date: Thu, 21 Jul 2011 10:46:13 -0500
>> From: Steve Stallings<[email protected]>
>> Reply-To: EMC developers<[email protected]>
>> To: 'EMC developers'<[email protected]>
>> Subject: Re: [Emc-developers] Preempt-RT ... where to put the patches ?
>>
>> Peter,
>>
>> Good point about interrupt jitter mattering less if
>> the actual sample time does not jitter. Unfortunately
>> the current RTAI setup requires that the interrupt
>> comes from the host interrupt timers. If we could
>> get to a system model where the hardware could
>> sample the data at the same time that it also
>> requests an interrupt, then the actual interrupt
>> latency would be much less critical. The PC system
>> design does not bring out the interrupt request
>> anywhere, so syncing with it in hardware is not
>> possible, nor can RTAI (as best I know) accept an
>> interrupt from external hardware as the system timer.
>>      
>
> What I was thinking about is living with the jitter, that is changing the math
> so that jitter is compensated for. This mostly means that any time the
> constant thread time is used in a PID/stepgen/motion calculations, the actual
> thread actuation time is used (jitter and all). That is if we can measure the
> jitter (we have a low overhead high resolution timer to read) we can
> compensate for it.
>
> For servo systems (or pseudo servo systems like hardware stepgens) jitter
> should really only cause second order errors ( commanded accell errors not
> velocity errors)
>
> As it is (without actual thread time factored in) even in an unaccelerated
> portion of a motion profile, a 10% jitter (say the D510s 100 Usec at a 1 KHz
> thread time) will cause the PID loop to see a 10 % velocity error (when in
> fact there may be no error at all).
>
>
>    
So basically you could factor out the jitter entirely?

That sounds like a really good idea!  :-)

Dave

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