I am trying to do something similar with a clocked output buffer ( USB ) ,
the USB chip clocks out the data from an internally clocked buffer, this way
I get 100% accuracy on the pulses to the steppers, only way to do USB .
You could turn it around, let EMC output 'next' data to a buffer, the
hardware poll it , deliver position and set interrupt, then you would have
overshoot detection :-D
/ regards, Lars
2011/7/21 Steve Stallings <steve...@newsguy.com>
> Peter,
>
> Good point about interrupt jitter mattering less if
> the actual sample time does not jitter. Unfortunately
> the current RTAI setup requires that the interrupt
> comes from the host interrupt timers. If we could
> get to a system model where the hardware could
> sample the data at the same time that it also
> requests an interrupt, then the actual interrupt
> latency would be much less critical. The PC system
> design does not bring out the interrupt request
> anywhere, so syncing with it in hardware is not
> possible, nor can RTAI (as best I know) accept an
> interrupt from external hardware as the system timer.
>
> I wonder if Preempt-RT may be more flexible.
>
> Steve Stallings (unrepentant top poster)
>
> -----Original Message-----
> From: Peter C. Wallace [mailto:p...@mesanet.com]
> Sent: Thursday, July 21, 2011 9:34 AM
> To: EMC developers
> Subject: Re: [Emc-developers] Preempt-RT ... where to put the patches ?
>
> On Wed, 20 Jul 2011, Jon Elson wrote:
>
> > Date: Wed, 20 Jul 2011 20:41:44 -0500
> > From: Jon Elson <el...@pico-systems.com>
> > Reply-To: EMC developers <emc-developers@lists.sourceforge.net>
> > To: EMC developers <emc-developers@lists.sourceforge.net>
> > Subject: Re: [Emc-developers] Preempt-RT ... where to put the patches ?
> >
> > Viesturs L cis wrote:
> > Out of curiosity I tried to find results for D510 and D525 boards -
> > they both are mentioned in the list of tested systems.
> >
> > This is D510:
> >
>
> https://www.osadl.org/Latency-plot-of-system-in-rack-1-slot.qa-latencyplot-r
> 1s4.0.html?latencies=&showno=&slider=228
> >
> > This is D525:
> >
>
> https://www.osadl.org/Latency-plot-of-system-in-rack-4-slot.qa-latencyplot-r
> 4s7.0.html?latencies=&showno=&slider=228
> >
> >
> > Where did they get 4 cores? From hyperthreading? Do I understand
> > correctly that disabling hyperthreading should improve latency
> > figures?
> >Yup, the D510 is a CATASTROPHE, the D525 is just really bad. You could
> >probably run a servo machine
>
> Well 100 uSec of jitter should be perfectly acceptable _if_ the PID
> (or hardware stepgen) corrections were based on actual time instead of
> thread
> invocation time, heck even 500 uSec jitter might be OK.
>
>
> >on the D525, but it isn't real good. Yes, I think the extra "CPUs" are
> >from hyperthreading, and disabling
> >it should help.
> >
> >Jon
>
>
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Unified Communications promises greater efficiencies for business. UC can
improve internal communications as well as offer faster, more efficient ways
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