-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 2/6/2013 6:51 AM, EBo wrote: > What are the max switching speed of both PRU and GPIO pins?
The PRU I/O pins can switch state every 5 nS, so a 10 nS cycle or generating a 100 MHz clock. The GPIO pins can be written by the 700+ MHz ARM CPU, but they apparently don't track changes that fast. Really, how deterministic the pin updates can be seems more important than the ultimate frequency, at least for step/dir control. The PRU I/O have essentially zero jitter. They can be read or updated by the PRU in one clock cycle, and the PRU itself is a deterministic, non-pipelined design. The GPIO pins can be accessed by the ARM core (subject to Linux latency jitter) or the PRU. When being accessed by the PRU they have substantially worse performance than the dedicated PRU I/O pins, as the bus transaction has to traverse the SoC interconnect fabric (arbitrating for access in the process), but it's still a lot less timing jitter than doing anything from Linux with the ARM core. So in short: PRU accessing dedicated PRU I/O: 5 nS timing granularity PRU accessing general purpose I/O: tens of nS granularity ARM core with Linux+Xenomai accessing GPIO: apx. 50 uS granularity ARM core with Linux accessing GPIO: up to 100s of mS granularity - -- Charles Steinkuehler char...@steinkuehler.net -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (MingW32) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iEYEARECAAYFAlESYcQACgkQLywbqEHdNFxlhQCg5LJ/HRLvmy9U0vGgBPpBbZ5w gPAAnihDLwgIYaHtiseiF984he/7xJUH =DzK8 -----END PGP SIGNATURE----- ------------------------------------------------------------------------------ Free Next-Gen Firewall Hardware Offer Buy your Sophos next-gen firewall before the end March 2013 and get the hardware for free! Learn more. http://p.sf.net/sfu/sophos-d2d-feb _______________________________________________ Emc-developers mailing list Emc-developers@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-developers