On 24 April 2011 16:32, Peter C. Wallace <[email protected]> wrote: > For bare Hbridges the U/V/W are offset so that 0 drive means all PWMS are set > to 50%. Does the BLDC component set this offset or is it in TPPWM?
bldc outputs three signed values. The offset is handled in tppwmgen. This would actually work with conventional PWMgens too, as it is effectively two analogue voltages so the PWM phasing isn't important. You would need to offset in HAL if that is required. There is a 6-wire output mode for bldc with individual positive and negative PWMs for each channel. -- atp "Torque wrenches are for the obedience of fools and the guidance of wise men" ------------------------------------------------------------------------------ Fulfilling the Lean Software Promise Lean software platforms are now widely adopted and the benefits have been demonstrated beyond question. Learn why your peers are replacing JEE containers with lightweight application servers - and what you can gain from the move. http://p.sf.net/sfu/vmware-sfemails _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
