I'm attaching the dmesg output so you can see what I'm talking about. El sáb., 7 mar. 2020 a las 10:20, Leonardo Marsaglia (<ldmarsag...@gmail.com>) escribió:
> Hello again to all, > > I'm reviving this discussion because I started attempting to configure my > setup to finally mount it on the machine (once it all works well off > course). > > Basically I'm using the 6i24 connected to a 7i52s for step output and to > read 1 encoder. Here's where I have the first doubts, mostly because I > don't do this too often. > > If I want to use the full 6 stepgens and 6 encoder inputs of the bitfile > Peter made for my 6i24 I see on the dmesg that the encoder and stepens are > distributed between P3 and P4 of the board. Is this ok? Because the 7i52s > as you know only has one 50 pin flat cable port. I'm not planning to use > that much encoders and steppers but this guides me to the next question. > > Is there an easy way to see the correspondence between the pins on the > 6i24 and the ones on the 7i52s ? Because if I use only 3 stepgens and 1 > encoder I can see they are all in the P4 connector and I have also some > free I/Os on that connector too but I don't know how to identify them on > the 7i52s other than start probing them one by one. > > Besides that, I need to modify the PIN file since I need the 7i52s to be > plugged to P1 connector of the 6i24 (Notice that the 6i24 has three ports > labelled P1, P3, P4). I'm downloading Xilinx ISE 14.7 to try to modify the > original file that Peter made for me. > > Well, that's all for now, if you can help me a little bit I surely can > make all this work this weekend hopefully. I also need to try the 7i44 but > I need to understand this first. > > Thanks as always for your help and patience! > > El jue., 19 dic. 2019 a las 8:54, andy pugh (<bodge...@gmail.com>) > escribió: > >> On Wed, 18 Dec 2019 at 22:32, Leonardo Marsaglia <ldmarsag...@gmail.com> >> wrote: >> >> > Also thanks for the source files, I'll use them to compare with the >> others >> > and try to understand better how to make my own bit files. >> >> Just to clarify (for other readers, as you probably know this). If the >> stepgen and encoder numbers are limited below maximum in the loadrt >> hm2_pci line in the HAL then their pins revert to GPIO. >> (But with so much smart-serial available, there is probably no reason >> to use them) >> >> My lathe uses a 6i24, with a 7i44 and 7i49. That leaves one spare >> 50-pin header. But with a 7i84 and 7i73 on the 7i44 that port is very >> much spare. >> >> (wandering off topic) >> The ultimate retrofit kit now would seem to be a combination of 7i94 >> and STMBL drives. >> Ethernet out of the PC, and digital end-to-end >> >> -- >> atp >> "A motorcycle is a bicycle with a pandemonium attachment and is >> designed for the especial use of mechanical geniuses, daredevils and >> lunatics." >> — George Fitch, Atlanta Constitution Newspaper, 1912 >> >> >> _______________________________________________ >> Emc-users mailing list >> Emc-users@lists.sourceforge.net >> https://lists.sourceforge.net/lists/listinfo/emc-users >> >
[ 978.261733] I-pipe: head domain RTAI registered. [ 978.261741] RTAI[hal]: compiled with gcc version 4.7.2 (Debian 4.7.2-5) . [ 978.261795] RTAI[hal]: mounted (IPIPE-NOTHREADS, IMMEDIATE (INTERNAL IRQs DISPATCHED), ISOL_CPUS_MASK: 0). [ 978.261799] SYSINFO: CPUs 2, LINUX APIC IRQ 2312, TIM_FREQ 6233920, CLK_FREQ 2992478000, CPU_FREQ 2992478000 [ 978.261802] RTAI_APIC_TIMER_IPI: RTAI DEFINED 2314, VECTOR 2314; LINUX_APIC_TIMER_IPI: RTAI DEFINED 2312, VECTOR 2312 [ 978.261805] TIMER NAME: lapic; VARIOUSLY FOUND APIC FREQs: 6233920, 6233920, 6220000 [ 978.269646] RTAI[malloc]: global heap size = 2097152 bytes, <BSD>. [ 978.269685] , <uses LINUX SYSCALLs>, kstacks pool size = 524288 bytes. [ 978.269689] RTAI[sched]: hard timer type/freq = APIC/6233920(Hz); default timing: oneshot; linear timed lists. [ 978.269692] RTAI[sched]: Linux timer freq = 250 (Hz), TimeBase freq = 2992478000 hz. [ 978.269694] RTAI[sched]: timer setup = 999 ns, resched latency = 2944 ns. [ 978.277250] RTAI[math]: loaded. [ 982.498867] hm2: loading Mesa HostMot2 driver version 0.15 [ 986.675658] hm2_pci: loading Mesa AnyIO HostMot2 driver version 0.7 [ 986.675700] hm2_pci: discovered 5i24 at 0000:04:00.0 [ 986.677943] hm2/hm2_5i24.0: Smart Serial Firmware Version 43 [ 986.743551] hm2/hm2_5i24.0: 72 I/O Pins used: [ 986.743556] hm2/hm2_5i24.0: IO Pin 000 (P4-01): IOPort [ 986.743560] hm2/hm2_5i24.0: IO Pin 001 (P4-03): Muxed Encoder #0, pin Muxed A (Input) [ 986.743563] hm2/hm2_5i24.0: IO Pin 002 (P4-05): Muxed Encoder #0, pin Muxed B (Input) [ 986.743566] hm2/hm2_5i24.0: IO Pin 003 (P4-07): Muxed Encoder #0, pin Muxed Index (Input) [ 986.743569] hm2/hm2_5i24.0: IO Pin 004 (P4-09): Muxed Encoder #1, pin Muxed A (Input) [ 986.743572] hm2/hm2_5i24.0: IO Pin 005 (P4-11): Muxed Encoder #1, pin Muxed B (Input) [ 986.743575] hm2/hm2_5i24.0: IO Pin 006 (P4-13): Muxed Encoder #1, pin Muxed Index (Input) [ 986.743578] hm2/hm2_5i24.0: IO Pin 007 (P4-15): Muxed Encoder #2, pin Muxed A (Input) [ 986.743580] hm2/hm2_5i24.0: IO Pin 008 (P4-17): Muxed Encoder #2, pin Muxed B (Input) [ 986.743583] hm2/hm2_5i24.0: IO Pin 009 (P4-19): Muxed Encoder #2, pin Muxed Index (Input) [ 986.743586] hm2/hm2_5i24.0: IO Pin 010 (P4-21): Muxed Encoder Select #0, pin Mux Select 0 (Output) [ 986.743589] hm2/hm2_5i24.0: IO Pin 011 (P4-23): StepGen #5, pin Step (Output) [ 986.743592] hm2/hm2_5i24.0: IO Pin 012 (P4-25): StepGen #5, pin Direction (Output) [ 986.743595] hm2/hm2_5i24.0: IO Pin 013 (P4-27): StepGen #4, pin Step (Output) [ 986.743598] hm2/hm2_5i24.0: IO Pin 014 (P4-29): StepGen #4, pin Direction (Output) [ 986.743600] hm2/hm2_5i24.0: IO Pin 015 (P4-31): StepGen #3, pin Step (Output) [ 986.743603] hm2/hm2_5i24.0: IO Pin 016 (P4-33): StepGen #3, pin Direction (Output) [ 986.743606] hm2/hm2_5i24.0: IO Pin 017 (P4-35): StepGen #2, pin Step (Output) [ 986.743608] hm2/hm2_5i24.0: IO Pin 018 (P4-37): StepGen #2, pin Direction (Output) [ 986.743611] hm2/hm2_5i24.0: IO Pin 019 (P4-39): StepGen #1, pin Step (Output) [ 986.743614] hm2/hm2_5i24.0: IO Pin 020 (P4-41): StepGen #1, pin Direction (Output) [ 986.743616] hm2/hm2_5i24.0: IO Pin 021 (P4-43): StepGen #0, pin Step (Output) [ 986.743619] hm2/hm2_5i24.0: IO Pin 022 (P4-45): StepGen #0, pin Direction (Output) [ 986.743621] hm2/hm2_5i24.0: IO Pin 023 (P4-47): IOPort [ 986.743623] hm2/hm2_5i24.0: IO Pin 024 (P3-01): IOPort [ 986.743626] hm2/hm2_5i24.0: IO Pin 025 (P3-03): Muxed Encoder #3, pin Muxed A (Input) [ 986.743628] hm2/hm2_5i24.0: IO Pin 026 (P3-05): Muxed Encoder #3, pin Muxed B (Input) [ 986.743631] hm2/hm2_5i24.0: IO Pin 027 (P3-07): Muxed Encoder #3, pin Muxed Index (Input) [ 986.743634] hm2/hm2_5i24.0: IO Pin 028 (P3-09): Muxed Encoder #4, pin Muxed A (Input) [ 986.743636] hm2/hm2_5i24.0: IO Pin 029 (P3-11): Muxed Encoder #4, pin Muxed B (Input) [ 986.743639] hm2/hm2_5i24.0: IO Pin 030 (P3-13): Muxed Encoder #4, pin Muxed Index (Input) [ 986.743642] hm2/hm2_5i24.0: IO Pin 031 (P3-15): Muxed Encoder #5, pin Muxed A (Input) [ 986.743644] hm2/hm2_5i24.0: IO Pin 032 (P3-17): Muxed Encoder #5, pin Muxed B (Input) [ 986.743647] hm2/hm2_5i24.0: IO Pin 033 (P3-19): Muxed Encoder #5, pin Muxed Index (Input) [ 986.743649] hm2/hm2_5i24.0: IO Pin 034 (P3-21): Muxed Encoder Select #6, pin Mux Select 0 (Output) [ 986.743652] hm2/hm2_5i24.0: IO Pin 035 (P3-23): StepGen #11, pin Step (Output) [ 986.743655] hm2/hm2_5i24.0: IO Pin 036 (P3-25): StepGen #11, pin Direction (Output) [ 986.743658] hm2/hm2_5i24.0: IO Pin 037 (P3-27): StepGen #10, pin Step (Output) [ 986.743660] hm2/hm2_5i24.0: IO Pin 038 (P3-29): StepGen #10, pin Direction (Output) [ 986.743663] hm2/hm2_5i24.0: IO Pin 039 (P3-31): StepGen #9, pin Step (Output) [ 986.743666] hm2/hm2_5i24.0: IO Pin 040 (P3-33): StepGen #9, pin Direction (Output) [ 986.743668] hm2/hm2_5i24.0: IO Pin 041 (P3-35): StepGen #8, pin Step (Output) [ 986.743671] hm2/hm2_5i24.0: IO Pin 042 (P3-37): StepGen #8, pin Direction (Output) [ 986.743674] hm2/hm2_5i24.0: IO Pin 043 (P3-39): StepGen #7, pin Step (Output) [ 986.743676] hm2/hm2_5i24.0: IO Pin 044 (P3-41): StepGen #7, pin Direction (Output) [ 986.743678] hm2/hm2_5i24.0: IO Pin 045 (P3-43): StepGen #6, pin Step (Output) [ 986.743681] hm2/hm2_5i24.0: IO Pin 046 (P3-45): StepGen #6, pin Direction (Output) [ 986.743683] hm2/hm2_5i24.0: IO Pin 047 (P3-47): IOPort [ 986.743685] hm2/hm2_5i24.0: IO Pin 048 (P2-01): IOPort [ 986.743688] hm2/hm2_5i24.0: IO Pin 049 (P2-03): IOPort [ 986.743690] hm2/hm2_5i24.0: IO Pin 050 (P2-05): IOPort [ 986.743692] hm2/hm2_5i24.0: IO Pin 051 (P2-07): IOPort [ 986.743694] hm2/hm2_5i24.0: IO Pin 052 (P2-09): IOPort [ 986.743696] hm2/hm2_5i24.0: IO Pin 053 (P2-11): IOPort [ 986.743698] hm2/hm2_5i24.0: IO Pin 054 (P2-13): IOPort [ 986.743700] hm2/hm2_5i24.0: IO Pin 055 (P2-15): IOPort [ 986.743702] hm2/hm2_5i24.0: IO Pin 056 (P2-17): IOPort [ 986.743704] hm2/hm2_5i24.0: IO Pin 057 (P2-19): IOPort [ 986.743706] hm2/hm2_5i24.0: IO Pin 058 (P2-21): IOPort [ 986.743708] hm2/hm2_5i24.0: IO Pin 059 (P2-23): IOPort [ 986.743710] hm2/hm2_5i24.0: IO Pin 060 (P2-25): IOPort [ 986.743712] hm2/hm2_5i24.0: IO Pin 061 (P2-27): IOPort [ 986.743715] hm2/hm2_5i24.0: IO Pin 062 (P2-29): IOPort [ 986.743717] hm2/hm2_5i24.0: IO Pin 063 (P2-31): IOPort [ 986.743719] hm2/hm2_5i24.0: IO Pin 064 (P2-33): IOPort [ 986.743721] hm2/hm2_5i24.0: IO Pin 065 (P2-35): IOPort [ 986.743723] hm2/hm2_5i24.0: IO Pin 066 (P2-37): IOPort [ 986.743725] hm2/hm2_5i24.0: IO Pin 067 (P2-39): IOPort [ 986.743727] hm2/hm2_5i24.0: IO Pin 068 (P2-41): IOPort [ 986.743729] hm2/hm2_5i24.0: IO Pin 069 (P2-43): IOPort [ 986.743731] hm2/hm2_5i24.0: IO Pin 070 (P2-45): IOPort [ 986.743733] hm2/hm2_5i24.0: IO Pin 071 (P2-47): IOPort [ 986.743932] hm2/hm2_5i24.0: registered [ 986.743935] hm2_5i24.0: initialized AnyIO board at 0000:04:00.0
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