[Bug tree-optimization/122635] RISC-V: -mrvv-vector-bits=zvl introducing unoptimal vsetivli zero,0 and insns depending on AVL nops

[gkm at rivosinc dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122635

--- Comment #16 from Greg McGary <gkm at rivosinc dot com> ---
(In reply to Jeffrey A. Law from comment #15)
> Though as Robin noted, it can be tackled in DSE as well.  We ought to be
> able to elide any zero length stores.  We typically have a DCE pass after
> DSE to clean up statements that were feeding the dead store.

DSE is good for stores, but we must also deal with loads.