[Bug tree-optimization/122635] RISC-V: -mrvv-vector-bits=zvl introducing unoptimal vsetivli zero,0 and insns depending on AVL nops

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122635

--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
The options for future reference:
`-march=rv64gcv_zvl256b -mabi=lp64d -Ofast -ftree-vectorize
-mrvv-vector-bits=zvl -funsigned-char`

Since I was looking for them and didn't realize they were only in godbolt link
:).