[Bug tree-optimization/122635] RISC-V: -mrvv-vector-bits=zvl introducing unoptimal vsetivli zero,0 and insns depending on AVL nops

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122635

--- Comment #7 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
The load/load that does not matter as they do at most 0 elements (0+0):
```
  vect__6.15_47 = .MASK_LEN_LOAD (vectp_e.12_45, 32B, { -1, -1, -1, -1, -1, -1,
-1, -1 }, _46(D), 0, 0);

...
  .MASK_LEN_STORE (vectp_e.12_45, 32B, { -1, -1, -1, -1, -1, -1, -1, -1 }, 0,
0, vect__8.18_54);
```