[Bug tree-optimization/122635] RISC-V: -mrvv-vector-bits=zvl introducing unoptimal vsetivli zero,0 and insns depending on AVL nops

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122635

--- Comment #8 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
>From IRC:
[18:51] <pinskia> I suspect the easy way is to add some simple code to
gimple-fold.cc that changes the MASK_LEN_STORE that has both 0s as arguments to
a GIMPLE_NOP or 
[18:52] <pinskia> you could also look into doing in tree-ssa-dce.cc marking
that stmt as not neede