Le 2014-04-29 11:15, Daniel Kho a écrit :
Hi yg,
Hi Daniel,
Does mcode+ really work this way? Sorry I'm not sure how this whole
thing works. If mcode+ is able to generate gate-level netlist for us,
that would be great. But does it do that really?
mcode does not work this way, but it is the closest to what I think is
required. At first I thought that I needed to create a new language
that would be a 3rd target of GHDL (after mcode and GCC) but I realised
yesterday that most of the work was already done on mcode :-)
the idea is to supplement the mcode generator with a parallel operation.
As far as I understand, when you add two integers, the mcode emits
a "add" instruction for the host CPU. So the idea is that
mcode+ would also emit, in parallel, a "add integer" node in a graph.
Say you have a
process with if-else statements, some gates, and a clock. Would mcode+
generate an equivalent gate-level circuit connecting each of these
components correctly in the form of a netlist? It requires quite some
amount of semantic analysis in my opinion. E.g.:
the funny part is that semantic analysis could be moved to the optimiser
:-)
the question is not "what the coder has in mind" but "what does it do",
in terms of actual gates, which is rather limited in fact
(boolean and sequential operations)
/* Input behavioural VHDL */
process(reset,clk) is begin
if reset then q<='0';
elsif rising_edge(clk) then q<=a xor b;
end if;
end process;
q<=a xor b is directly mapped to a gate or macro-gate if it's a vector.
the "if" are branches in the graph, controlled by the conditions.
At a later stage, you then apply the usual transformation rules :
- conditions that use a clock edge should be DFF
- conditions that use a level but no "else" are latches
- conditions with ELSE are logic.
I would expect a generated netlist to look something like (structural
VHDL here, but could be in any other language):
-- example output gate-level netlist
<...>
If mcode+ is able to do this, it's something worth taking a look. :)
it's not doing this, but it's the closest language that I believe one
could
"piggy back" upon, since it is already functional.
How about having case statements, if-elsif-else, of with-select-when
statements? We need something that automatically creates the muxes.
muxes are infered from the "if" rules i explained above.
the synthesiser/mapper has to select the proper function but it's not
the
hard part. the fist step is to extract actual functions from the code,
and "high level code" can contain actual code in weird places like
in package headers and such... places that basic synthesisers don't look
at.
I too would like to have a free (and open source) VHDL compliant
synthesis tool. :)
what would you do with it ? :-)
regards, daniel
cheers, yg
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