Hi yg, How about having case statements, if-elsif-else, of with-select-when >> statements? We need something that automatically creates the muxes. >> > muxes are infered from the "if" rules i explained above. > the synthesiser/mapper has to select the proper function but it's not the > hard part. the fist step is to extract actual functions from the code, > and "high level code" can contain actual code in weird places like > in package headers and such... places that basic synthesisers don't look > at.
If we could generate gate-level structural code out of these basic rules [clocks, conditionals (if-elsif-else, case, with-select-when), and logic], I think that's a good start. For more abstract things like type/package/subprogram generics, or packages, configurations, etc., perhaps this is where the presynthesis tool (converts between the more abstract VHDL-2008 to simple VHDL-93) kicks in. I could help in this area. Some things, for example configurations, just tell the synthesis tool which architecture to synthesise, so our pre-compiler could figure that out and generate the simple VHDL-93 code without configurations, instead using a fixed architecture for example. Same thing goes for generic types - our pre-compiler can set the types to fixed values based on what's been selected by the user at the top level of the design. > I too would like to have a free (and open source) VHDL compliant >> synthesis tool. :) >> > what would you do with it ? :-) > I now maintain two copies of all my work that need to be synthesised. One version is the more readable VHDL-2008 version, and another is the more bloated '93 version. I hope to ditch the '93 version for good, and not have to worry about such conversions in future. cheers, dan
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