On Fri, Aug 7, 2009 at 5:52 AM, Iljitsch van Beijnum<iljit...@muada.com> wrote: > On 5 aug 2009, at 19:34, Christopher Morrow wrote: > >> You may see 2-3 year cycle on new asics for this feature to appear... >> given 1-2 years for haggling/bugs/blah it's safe to say 3-5 yrs before >> hardware is on the shelf to purchase. > > You assume this requires new hardware. Although that's not inconceivable, I > would think that in most cases a software or microcode update would be > sufficient.
I look forward to your microcode update ... I'm not sure that classifiers (on juniper or cisco devices) that work at 40g+ are going to be microcode upgradable. My point is that just saying: "Well, now use X. See all fixed!" isn't reality. There is atleast a 3-5 year lag. >> 'flow label bits alone make a poor material for a hash key'... isn't >> this the reverse of saying that we'll (operators) require vendors to >> use flow-label for hashing on ECMP/LAG? If so, then... I don't think >> flow-label's going to cut it. > > Huh? > brian sufficiently cleared up the wording/reasoning. > By the way, if we want good load balancing in IPv6 it's always possible to > use more source/destination address pairs, as addresses are cheap in IPv6. awesome, how do I do that dynamically and on-demand? you're imposing a restriction on the end users in order to fix this core problem, outside of LISP I mean, I'm not sure that's going to work out either (shifting costs and such). -chris -------------------------------------------------------------------- IETF IPv6 working group mailing list ipv6@ietf.org Administrative Requests: https://www.ietf.org/mailman/listinfo/ipv6 --------------------------------------------------------------------
