Hi Oliver
I got the checker board shown in wave :). The problem seems to bee
missing VERT_RESULT_BFC0.
I have attached a patch that gets VERT_RESULT_BFC0 a step closer.
There is a couple of problems:
1) This patch makes the driver do state changes allot.
2) I fink there is something more basic wrong wit how wee handle
VERT_RESULT.
How do the chip now that the reg wee set in r300TranslateVertexShader
with code like:
vp->outputs[VERT_RESULT_BFC0] = cur_reg++;
is for VERT_RESULT_BFC0.
Any insights?
The patch makes the tube in fog look read instead of green. NWN looks as
it has for some time. OK but with weird colors on cloaks an some
monsters.
I am going to keep looking.
/Tommy
diff --git a/src/mesa/drivers/dri/r300/r300_emit.c b/src/mesa/drivers/dri/r300/r300_emit.c
index 4670c28..907da26 100644
--- a/src/mesa/drivers/dri/r300/r300_emit.c
+++ b/src/mesa/drivers/dri/r300/r300_emit.c
@@ -299,13 +309,13 @@ static GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten)
if (OutputsWritten & (1 << VERT_RESULT_COL1))
ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT;
-#if 0
if (OutputsWritten & (1 << VERT_RESULT_BFC0))
- ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT;
+ ret |= (1 << 16);
if (OutputsWritten & (1 << VERT_RESULT_BFC1))
- ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT;
+ ret |= (1 << 17);
+#if 0
if (OutputsWritten & (1 << VERT_RESULT_FOGC)) ;
#endif
diff --git a/src/mesa/drivers/dri/r300/r300_vertprog.c b/src/mesa/drivers/dri/r300/r300_vertprog.c
index 16dddf6..1cb25b8 100644
--- a/src/mesa/drivers/dri/r300/r300_vertprog.c
+++ b/src/mesa/drivers/dri/r300/r300_vertprog.c
@@ -441,41 +441,49 @@ static void r300TranslateVertexShader(struct r300_vertex_program *vp,
if (vp->key.OutputsWritten & (1 << VERT_RESULT_HPOS))
vp->outputs[VERT_RESULT_HPOS] = cur_reg++;
- if (vp->key.OutputsWritten & (1 << VERT_RESULT_PSIZ))
- vp->outputs[VERT_RESULT_PSIZ] = cur_reg++;
-
if (vp->key.OutputsWritten & (1 << VERT_RESULT_COL0))
vp->outputs[VERT_RESULT_COL0] = cur_reg++;
if (vp->key.OutputsWritten & (1 << VERT_RESULT_COL1))
vp->outputs[VERT_RESULT_COL1] = cur_reg++;
-#if 0 /* Not supported yet */
- if (vp->key.OutputsWritten & (1 << VERT_RESULT_BFC0))
- vp->outputs[VERT_RESULT_BFC0] = cur_reg++;
-
- if (vp->key.OutputsWritten & (1 << VERT_RESULT_BFC1))
- vp->outputs[VERT_RESULT_BFC1] = cur_reg++;
+ if (vp->key.OutputsWritten & (1 << VERT_RESULT_PSIZ))
+ vp->outputs[VERT_RESULT_PSIZ] = cur_reg++;
+#if 0 /* Not supported yet */
if (vp->key.OutputsWritten & (1 << VERT_RESULT_FOGC))
- vp->outputs[VERT_RESULT_FOGC] = cur_reg++;
+ vp->outputs[VERT_RESULT_FOGC] = VERT_RESULT_FOGC;
#endif
for (i = VERT_RESULT_TEX0; i <= VERT_RESULT_TEX7; i++)
if (vp->key.OutputsWritten & (1 << i))
vp->outputs[i] = cur_reg++;
+ vp->outputs[VERT_RESULT_BFC0] = cur_reg++;
+ vp->outputs[VERT_RESULT_BFC1] = cur_reg++;
+
vp->translated = GL_TRUE;
vp->native = GL_TRUE;
o_inst = vp->program.body.i;
for (; vpi->Opcode != OPCODE_END; vpi++, o_inst++) {
FREE_TEMPS();
if (!valid_dst(vp, &vpi->DstReg)) {
/* redirect result to unused temp */
vpi->DstReg.File = PROGRAM_TEMPORARY;
vpi->DstReg.Index = u_temp_i;
+ } else if (vp->outputs[vpi->DstReg.Index] != -1) {
+ if ((vpi->DstReg.Index == VERT_RESULT_BFC0) &&
+ !(vp->key.
+ OutputsWritten & (1 << VERT_RESULT_BFC0))) {
+ vp->key.OutputsWritten |= 1 << VERT_RESULT_BFC0;
+ } else if ((vpi->DstReg.Index == VERT_RESULT_BFC1) &&
+ !(vp->key.
+ OutputsWritten & (1 << VERT_RESULT_BFC1)))
+ {
+ vp->key.OutputsWritten |= 1 << VERT_RESULT_BFC1;
+ }
}
operands = op_operands(vpi->Opcode);
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