Regarding fading, I've seen clocks that gradually make 1 digit dimmer as the next digit becomes brighter (with overlap), and it looks more like a blurry mess. You may want to use PWM to dim the changing digit in a 100-200 msec, before you gradually turn-on the next value. It might be annoying for digits changing every second (or in your case, 1/10 second ??), but for tens-seconds and beyond it should look OK. None of the clocks I've built so far will support this, but the next one will be capable of it.
Based on the HV5530 driver, I'm assuming your clock is direct-drive, so you will have more options for effects. Did you add a level-shifter to drive the 5530's inputs at the recommended 12V signal-levels ? I'm also curious if you cascaded the serial data-in/data out signals if both 5530's use the same clock; per the datasheet, doing so is a timing risk (data-hold time is 10nsec, and there is no min-prop delay specified hence assume 0. This implies a 10nsec timing risk). I'm finalizing the PC board for my 14-digit IN-18 clock, and took no risks: Using a level-shifter, and separate clocks for each HV5530. I'm using an FPGA instead of a microcontroller, and I have enough room on the FPGA for a small CPU (probably Z80) if I decide to go that route instead of pure Verilog code. -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to neonixie-l+unsubscr...@googlegroups.com. To post to this group, send an email to neonixie-l@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/3e76599d-cfa9-4b47-af31-4d8060d21cb1%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
