On Saturday 10 June 2006 21:25, Jack Carroll wrote: > On Sat, Jun 10, 2006 at 05:58:48PM +0100, Hamish wrote: > > On Saturday 10 June 2006 16:40, Hamish wrote: > > > > [deleted] > > > > > In addition, should we be doing anything with the WP and HOLD pins of > > > the SPI? They don't seem to be defined as an output for the module like > > > the other SPI input pins... Is hold simply to be tied and WP jumpered? > > > Or something else? > > > > Ah. Found this bit in the RevB schematics... They appear to be tied to > > Vcc? No write protect then? Is there any advantage to connecting WP_ to > > the XP6? (Are there any pins free on the XP6 to tie it to? If the XP6 can > > come up with WP_ low, then we can prevent spurious code from over-writing > > the SPI by accident (Or at least till something calls a write_enable > > function first). > > I haven't looked at the OGD1 schematic or the EEPROM's data sheet. > However, this seems to say that the part has physical write protection, > controlled by a separate pin. (Most SPI EEPROMs don't, which has always > annoyed me.) If it does, may I suggest that the write protect pin be > connected to a header, so a jumper plug can disable it? That way, it can > be manually protected against runaway software.
Now that is a _really_ good idea. Is it too late to implement it? Maybe making a single jumper write-protect both PROMs would be a good way to do it... Timothy? Howard? Peter -- Quake II build tools maintainer http://tinyurl.com/fkldd v2sw6YShw7$ln5pr6ck3ma8u6/8Lw3+2m0l7Ci6e4+8t4Eb8Aen5+6g6Pa2Xs5MSr5p4 hackerkey.com
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