On Saturday 10 June 2006 14:16, Dieter wrote: > > may I suggest that the write protect pin be > > connected to a header, so a jumper plug can disable it? That way, it can > > be manually protected against runaway software. > > If the PROM contents are bad due to runaway software or whatever reason, > does the board become a doorstop, or is there a fail-safe method to > reprogram it?
If the PCI interface FPGA PROM is corrupted, it looks like you'll want to plug a JTAG configuration cable (from a different computer) onto J1 & J2[*] and blast a new core onto the FPGA, which will get the board working. Now, if the broken FPGA configuration in the PROM has hung the PCI bus on the development box, how do you reprogram the PROM without rebooting the system and thus reloading the corrupted image? The way Timothy's explained it seemed to indicate that you can only program the PROM over the PCI bus, so I must have misinterpreted him. :P Although I would have preferred it if they had used a Molex 87832-1420 or equivalent for the JTAG socket, I have a nice little ribbon cable from Xilinx that fits straight onto one of those! But don't forget that there are actually two PROMs, one for the little FPGA and one for the big FPGA. Normally you won't touch the small PROM, and just play around with the big one. So write-protect headers do make some sense. :) Peter [*] I can't see any silkscreen layer on the current artwork, but hopefully all the J1 & J2 will have the pins labelled TMS, TDI, TDO, TCK, or much confusion may well result. Also, the current artwork seems to show J1 & J2 in a block rather than in a line... if they're in a line it makes it a lot easier to interface a cable onto them IMHO. P.S. KPDF handles these big complex PDF files far better than Acrobat Reader does. :D -- Quake II build tools maintainer http://tinyurl.com/fkldd v2sw6YShw7$ln5pr6ck3ma8u6/8Lw3+2m0l7Ci6e4+8t4Eb8Aen5+6g6Pa2Xs5MSr5p4 hackerkey.com
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