On 5/27/2026 1:13 PM, Philippe Mathieu-Daudé wrote: > From: Djordje Todorovic <[email protected]> > > The page table walker reads PTEs using address_space_ldl/ldq which use > compile-time native endianness (always LE for RISC-V). However, when a > big-endian kernel writes PTEs via normal store instructions, they are > stored in big-endian byte order. The walker then misinterprets the PTE > values, causing page faults and a hang when the kernel enables the MMU. > > The RISC-V privileged specification states that implicit data memory > accesses to supervisor-level memory management data structures follow > the hart's endianness setting (MSTATUS SBE/MBE bits). > > Fix both PTE reads and atomic A/D bit updates to use the explicit _le > or _be memory access variants based on the hart's runtime endianness. > > Signed-off-by: Djordje Todorovic <[email protected]> > Reviewed-by: Philippe Mathieu-Daudé <[email protected]> > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > --- > target/riscv/cpu_helper.c | 19 +++++++++++-------- > 1 file changed, 11 insertions(+), 8 deletions(-) >
Reviewed-by: Pierrick Bouvier <[email protected]>
