On 5/27/2026 1:13 PM, Philippe Mathieu-Daudé wrote: > From: Djordje Todorovic <[email protected]> > > Add a big_endian field to RISCVCPUConfig and wire it into the CPU > reset path. When cfg.big_endian is set, riscv_cpu_reset_hold() > writes 1 into the MSTATUS MBE/SBE/UBE fields using set_field(); > otherwise it writes 0. This makes the reset value deterministic on > both cold and warm reset. > > This models fixed-endian harts, not mixed-endian implementations where > the guest can toggle MBE/SBE/UBE at runtime. The MBE/SBE/UBE bits are > not included in the writable mask of any mstatus/mstatush/sstatus CSR > write path (unchanged by this series), so the value chosen at reset is > effectively hardwired per section 3.1.6.5 of the RISC-V Privileged > Specification. > > The user-facing property and documentation are added in a later patch, > once the full endianness support is in place. > > Signed-off-by: Djordje Todorovic <[email protected]> > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > --- > target/riscv/cpu_cfg_fields.h.inc | 1 + > target/riscv/cpu.c | 7 +++++++ > 2 files changed, 8 insertions(+) >
Reviewed-by: Pierrick Bouvier <[email protected]>
