The e6500 L1 instruction and data caches use 64-byte cache lines. The cache configuration registers already describe this geometry, but the translator used 32-byte lines for cache operations.
Match the line sizes to the hardware so that guest cache management and dcbz agree with the reported configuration. Reference: E6500RM (Rev.0), section 2.11.4 and 2.11.5 https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf Fixes: 54a50dae93fa ("ppc64: introduce e6500") Cc: [email protected] Signed-off-by: Bin Meng <[email protected]> --- target/ppc/cpu_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index db807f64c2..29f28be7e0 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2890,8 +2890,8 @@ static void init_proc_e500(CPUPPCState *env, int version) l1cfg1 |= 0x00800000; /* 64 byte cache block size */ break; case fsl_e6500: - env->dcache_line_size = 32; - env->icache_line_size = 32; + env->dcache_line_size = 64; + env->icache_line_size = 64; l1cfg0 |= 0x0F83820; l1cfg1 |= 0x0B83820; break; -- 2.53.0
