Annotate the GICv5 system insn cpreg structs with the fine-grained trap information. This covers all the bits in ICH_HFGITR_EL2.
Signed-off-by: Peter Maydell <[email protected]> --- target/arm/tcg/gicv5-cpuif.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index a829b90f334..be34312d242 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -800,56 +800,67 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { { .name = "GIC_CDDIS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_GICCDDIS, .writefn = gic_cddis_write, }, { .name = "GIC_CDEN", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1, .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_GICCDEN, .writefn = gic_cden_write, }, { .name = "GIC_CDPRI", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 2, .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_GICCDPRI, .writefn = gic_cdpri_write, }, { .name = "GIC_CDAFF", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 3, .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_GICCDAFF, .writefn = gic_cdaff_write, }, { .name = "GIC_CDPEND", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 4, .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_GICCDPEND, .writefn = gic_cdpend_write, }, { .name = "GIC_CDRCFG", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 5, .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_GICCDRCFG, .writefn = gic_cdrcfg_write, }, { .name = "GIC_CDEOI", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 7, .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_GICCDEOI, .writefn = gic_cdeoi_write, }, { .name = "GIC_CDDI", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 2, .opc2 = 0, .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_GICCDDI, .writefn = gic_cddi_write, }, { .name = "GIC_CDHM", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 2, .opc2 = 1, .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_GICCDHM, .writefn = gic_cdhm_write, }, { .name = "GICR_CDIA", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 3, .opc2 = 0, .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_GICRCDIA, .readfn = gicr_cdia_read, }, { .name = "GICR_CDNMIA", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 3, .opc2 = 1, .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fgt = FGT_GICRCDNMIA, .readfn = gicr_cdia_read, }, { .name = "ICC_IDR0_EL1", .state = ARM_CP_STATE_AA64, -- 2.43.0
