A typo in the definition of IRS_VMT_STATUSR made its offset 0x124 instead of the correct 0x214. This was harmless for our initial EL1-only GICv5, where the register doesn't exist, but needs to be fixed for virtualization support.
Signed-off-by: Peter Maydell <[email protected]> --- include/hw/intc/arm_gicv5_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/intc/arm_gicv5_regs.h b/include/hw/intc/arm_gicv5_regs.h index 275fee315b5..1d0fb8b147e 100644 --- a/include/hw/intc/arm_gicv5_regs.h +++ b/include/hw/intc/arm_gicv5_regs.h @@ -149,7 +149,7 @@ REG32(IRS_VMT_CFGR, 0x210) FIELD(IRS_VMT_CFGR, VM_ID_BITS, 0, 5) FIELD(IRS_VMT_CFGR, STRUCTURE, 16, 1) -REG32(IRS_VMT_STATUSR, 0x124) +REG32(IRS_VMT_STATUSR, 0x214) FIELD(IRS_VMT_STATUSR, IDLE, 0, 1) REG64(IRS_VPE_SELR, 0x240) -- 2.43.0
