The ICH_PPI_HVIR<n>_EL2 registers allow a hypervisor to hide a PPI from the virtual interrupt domain. When the bit is set, direct reads and writes to ICV register fields for that PPI are RAZ/WI.
As we haven't yet implemented the ICV accesses, all we need to implement here is the cpreg and its backing storage. We will then be able to test the DVI bits in the functions that add ICV read and write handling. We give the register a writefn because eventually it will need to trigger a recalculation of the virtual PPI HPPI. Signed-off-by: Peter Maydell <[email protected]> --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 276466d2b84..81fb68facb9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -600,6 +600,7 @@ typedef struct CPUArchState { uint64_t ich_apr_el2; uint64_t ich_vctlr_el2; uint64_t ich_vmcr_el2; + uint64_t ich_ppi_hvi[GICV5_NUM_PPIS / 64]; uint64_t ich_ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ich_ppi_pend[GICV5_NUM_PPIS / 64]; uint64_t ich_ppi_enable[GICV5_NUM_PPIS / 64]; diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 8cb790204f1..93141c751e4 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -493,6 +493,12 @@ static void gic_ich_ppi_dvi_write(CPUARMState *env, const ARMCPRegInfo *ri, raw_write(env, ri, value); } +static void gic_ich_ppi_hvi_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + static void gic_ich_vctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1002,6 +1008,22 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .writefn = gic_icc_pcr_el1_write, .resetfn = gic_icc_pcr_el1_reset, }, + { .name = "ICH_PPI_HVIR0_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 7, .opc2 = 0, + .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0xc00, + .accessfn = access_gicv5_ich_reg, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_ppi_hvi[0]), + .writefn = gic_ich_ppi_hvi_write, + }, + { .name = "ICH_PPI_HVIR1_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 7, .opc2 = 1, + .access = PL2_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset = 0xc00, + .accessfn = access_gicv5_ich_reg, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ich_ppi_hvi[1]), + .writefn = gic_ich_ppi_hvi_write, + }, { .name = "ICH_APR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 4, .access = PL2_RW, .type = ARM_CP_NO_RAW, -- 2.43.0
