From: Philippe Mathieu-Daudé <[email protected]> Replace runtime helpers by translation. BE LD.D/ST.D now uses MO_BE with exchanged half handles; no explicit D swaps or store-copy temporaries.
Replace the legacy cpu_ld/st*_data_ra() calls by tcg_gen_qemu_ld/st() which allow to respect atomicity. Remove the ensure_writable_pages() hack and MSALDST_PROTO macro. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/mips/tcg/msa_helper.h.inc | 6 --- target/mips/tcg/msa_helper.c | 63 -------------------------------- target/mips/tcg/msa_translate.c | 28 +++++--------- 3 files changed, 10 insertions(+), 87 deletions(-) diff --git a/target/mips/tcg/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc index f0d31ceef291..e994353056f7 100644 --- a/target/mips/tcg/msa_helper.h.inc +++ b/target/mips/tcg/msa_helper.h.inc @@ -432,9 +432,3 @@ DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32) - -#define MSALDST_PROTO(type) \ -DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \ -DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl) -MSALDST_PROTO(d) -#undef MSALDST_PROTO diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index afd9cca09604..9ef63b0e197e 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -21,11 +21,8 @@ #include "cpu.h" #include "internal.h" #include "tcg/tcg.h" -#include "accel/tcg/cpu-ldst.h" -#include "accel/tcg/probe.h" #include "exec/helper-proto.h" #include "exec/memop.h" -#include "exec/target_page.h" #include "fpu/softfloat.h" #include "fpu_helper.h" @@ -8219,63 +8216,3 @@ void HELPER(msa_ffint_u_df)(CPUMIPSState *env, uint32_t df, uint32_t wd, msa_move_v(pwd, pwx); } - -/* Data format min and max values */ -#define DF_BITS(df) (1 << ((df) + 3)) - -/* Element-by-element access macros */ -#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) - -void HELPER(msa_ld_d)(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - uintptr_t ra = GETPC(); - uint64_t d0, d1; - - if (mips_env_is_bigendian(env)) { - d0 = cpu_ldq_be_data_ra(env, addr + 0, ra); - d1 = cpu_ldq_be_data_ra(env, addr + 8, ra); - } else { - d0 = cpu_ldq_le_data_ra(env, addr + 0, ra); - d1 = cpu_ldq_le_data_ra(env, addr + 8, ra); - } - pwd->d[0] = d0; - pwd->d[1] = d1; -} - -#define MSA_PAGESPAN(x) \ - ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE) - -static inline void ensure_writable_pages(CPUMIPSState *env, - target_ulong addr, - int mmu_idx, - uintptr_t retaddr) -{ - /* FIXME: Probe the actual accesses (pass and use a size) */ - if (unlikely(MSA_PAGESPAN(addr))) { - /* first page */ - probe_write(env, addr, 0, mmu_idx, retaddr); - /* second page */ - addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - probe_write(env, addr, 0, mmu_idx, retaddr); - } -} - -void HELPER(msa_st_d)(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - int mmu_idx = mips_env_mmu_index(env); - uintptr_t ra = GETPC(); - - ensure_writable_pages(env, addr, mmu_idx, GETPC()); - - if (mips_env_is_bigendian(env)) { - cpu_stq_be_data_ra(env, addr + 0, pwd->d[0], ra); - cpu_stq_be_data_ra(env, addr + 8, pwd->d[1], ra); - } else { - cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra); - cpu_stq_le_data_ra(env, addr + 8, pwd->d[1], ra); - } -} diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 7a3c2390cfca..2d6f3d6070ba 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -785,8 +785,8 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load) MO_ATOM_NONE, MO_ATOM_SUBALIGN, /* Slightly stronger than required */ MO_ATOM_SUBALIGN, /* Slightly stronger than required */ + MO_ATOM_IFALIGN_PAIR }; - TCGv_i32 wd; TCGv_i128 t16; TCGv_va addr; MemOp mop; @@ -801,33 +801,25 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load) addr = tcgv_va_temp_new(); gen_base_offset_addr(ctx, addr, a->ws, a->sa << a->df); - wd = tcg_constant_i32(a->wd); - - if (is_load) { - switch (a->df) { - case 3: - gen_helper_msa_ld_d(tcg_env, wd, addr); - return true; - } - } else { - switch (a->df) { - case 3: - gen_helper_msa_st_d(tcg_env, wd, addr); - return true; - } - } - t16 = tcg_temp_new_i128(); mop = MO_128 | MO_LE; mop |= mo_atom_df[a->df]; + if (a->df == 3 && mo_endian(ctx) != MO_LE) { + TCGv_i64 saved_d0 = d0; + + mop = (mop & ~MO_BSWAP) | MO_BE; + d0 = d1; + d1 = saved_d0; + } + if (is_load) { tcg_gen_qemu_ld_i128(t16, addr, ctx->mem_idx, mop); tcg_gen_extr_i128_i64(d0, d1, t16); } - if (mo_endian(ctx) != MO_LE) { + if (mo_endian(ctx) != MO_LE && a->df != 3) { if (!is_load) { TCGv_i64 temp_d0 = tcg_temp_new_i64(); TCGv_i64 temp_d1 = tcg_temp_new_i64(); -- 2.55.0
