From: Philippe Mathieu-Daudé <[email protected]> Replace runtime helpers by translation.
Replace the legacy cpu_ld/st*_data_ra() calls by tcg_gen_qemu_ld/st() which allow to respect atomicity. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/mips/tcg/msa_helper.h.inc | 1 - target/mips/tcg/msa_helper.c | 47 -------------------------------- target/mips/tcg/msa_translate.c | 20 ++++++++++---- 3 files changed, 14 insertions(+), 54 deletions(-) diff --git a/target/mips/tcg/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc index 86a79bf804ce..f0d31ceef291 100644 --- a/target/mips/tcg/msa_helper.h.inc +++ b/target/mips/tcg/msa_helper.h.inc @@ -436,6 +436,5 @@ DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32) #define MSALDST_PROTO(type) \ DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \ DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl) -MSALDST_PROTO(w) MSALDST_PROTO(d) #undef MSALDST_PROTO diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 08c900785f9e..afd9cca09604 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8226,32 +8226,6 @@ void HELPER(msa_ffint_u_df)(CPUMIPSState *env, uint32_t df, uint32_t wd, /* Element-by-element access macros */ #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) -static inline uint64_t bswap32x2(uint64_t x) -{ - return ror64(bswap64(x), 32); -} - -void HELPER(msa_ld_w)(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - uintptr_t ra = GETPC(); - uint64_t d0, d1; - - /* - * Load 8 bytes at a time. Use little-endian load, then for - * big-endian target, we must then bswap the two words. - */ - d0 = cpu_ldq_le_data_ra(env, addr + 0, ra); - d1 = cpu_ldq_le_data_ra(env, addr + 8, ra); - if (mips_env_is_bigendian(env)) { - d0 = bswap32x2(d0); - d1 = bswap32x2(d1); - } - pwd->d[0] = d0; - pwd->d[1] = d1; -} - void HELPER(msa_ld_d)(CPUMIPSState *env, uint32_t wd, target_ulong addr) { @@ -8288,27 +8262,6 @@ static inline void ensure_writable_pages(CPUMIPSState *env, } } -void HELPER(msa_st_w)(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - int mmu_idx = mips_env_mmu_index(env); - uintptr_t ra = GETPC(); - uint64_t d0, d1; - - ensure_writable_pages(env, addr, mmu_idx, ra); - - /* Store 8 bytes at a time. See helper_msa_ld_w. */ - d0 = pwd->d[0]; - d1 = pwd->d[1]; - if (mips_env_is_bigendian(env)) { - d0 = bswap32x2(d0); - d1 = bswap32x2(d1); - } - cpu_stq_le_data_ra(env, addr + 0, d0, ra); - cpu_stq_le_data_ra(env, addr + 8, d1, ra); -} - void HELPER(msa_st_d)(CPUMIPSState *env, uint32_t wd, target_ulong addr) { diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 0c6c2f4551dc..7a3c2390cfca 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -770,11 +770,21 @@ static void gen_bswap16x4_i64(TCGv_i64 dst, TCGv_i64 src) tcg_gen_or_i64(dst, t0, t1); /* dst = badcfebg */ } +/* + * Byte pattern: abcd.efgh -> dcba.hgfe + */ +static void gen_bswap32x2_i64(TCGv_i64 dst, TCGv_i64 src) +{ + tcg_gen_bswap64_i64(dst, src); + tcg_gen_rotri_i64(dst, dst, 32); +} + static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load) { static const MemOp mo_atom_df[4] = { MO_ATOM_NONE, MO_ATOM_SUBALIGN, /* Slightly stronger than required */ + MO_ATOM_SUBALIGN, /* Slightly stronger than required */ }; TCGv_i32 wd; TCGv_i128 t16; @@ -795,18 +805,12 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load) if (is_load) { switch (a->df) { - case 2: - gen_helper_msa_ld_w(tcg_env, wd, addr); - return true; case 3: gen_helper_msa_ld_d(tcg_env, wd, addr); return true; } } else { switch (a->df) { - case 2: - gen_helper_msa_st_w(tcg_env, wd, addr); - return true; case 3: gen_helper_msa_st_d(tcg_env, wd, addr); return true; @@ -839,6 +843,10 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load) gen_bswap16x4_i64(d0, d0); gen_bswap16x4_i64(d1, d1); break; + case 2: + gen_bswap32x2_i64(d0, d0); + gen_bswap32x2_i64(d1, d1); + break; } } -- 2.55.0
