From: Philippe Mathieu-Daudé <[email protected]> Replace runtime helpers by translation.
Replace the legacy cpu_ld/st*_data_ra() calls by tcg_gen_qemu_ld/st() which allow to respect atomicity. Consider the host endianness. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/mips/tcg/msa_helper.h.inc | 1 - target/mips/tcg/msa_helper.c | 28 ---------------------------- target/mips/tcg/msa_translate.c | 29 +++++++++++++++++++++++------ 3 files changed, 23 insertions(+), 35 deletions(-) diff --git a/target/mips/tcg/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc index 4963d1553a09..50a2732e916a 100644 --- a/target/mips/tcg/msa_helper.h.inc +++ b/target/mips/tcg/msa_helper.h.inc @@ -436,7 +436,6 @@ DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32) #define MSALDST_PROTO(type) \ DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \ DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl) -MSALDST_PROTO(b) MSALDST_PROTO(h) MSALDST_PROTO(w) MSALDST_PROTO(d) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 1919ce6be9eb..70de98050cdc 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8237,20 +8237,6 @@ static inline uint64_t bswap32x2(uint64_t x) return ror64(bswap64(x), 32); } -void HELPER(msa_ld_b)(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - uintptr_t ra = GETPC(); - uint64_t d0, d1; - - /* Load 8 bytes at a time. Vector element ordering makes this LE. */ - d0 = cpu_ldq_le_data_ra(env, addr + 0, ra); - d1 = cpu_ldq_le_data_ra(env, addr + 8, ra); - pwd->d[0] = d0; - pwd->d[1] = d1; -} - void HELPER(msa_ld_h)(CPUMIPSState *env, uint32_t wd, target_ulong addr) { @@ -8329,20 +8315,6 @@ static inline void ensure_writable_pages(CPUMIPSState *env, } } -void HELPER(msa_st_b)(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - int mmu_idx = mips_env_mmu_index(env); - uintptr_t ra = GETPC(); - - ensure_writable_pages(env, addr, mmu_idx, ra); - - /* Store 8 bytes at a time. Vector element ordering makes this LE. */ - cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra); - cpu_stq_le_data_ra(env, addr + 8, pwd->d[1], ra); -} - void HELPER(msa_st_h)(CPUMIPSState *env, uint32_t wd, target_ulong addr) { diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index ab4b1998aa0b..b7ca352d07b6 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -756,8 +756,16 @@ TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load) { + static const MemOp mo_atom_df[4] = { + MO_ATOM_NONE, + }; TCGv_i32 wd; + TCGv_i128 t16; TCGv_va addr; + MemOp mop; + int idx = a->wd << 1; + TCGv_i64 d0 = msa_wr_d[idx + FP_ENDIAN_IDX]; + TCGv_i64 d1 = msa_wr_d[idx + !FP_ENDIAN_IDX]; if (!check_msa_enabled(ctx)) { return true; @@ -770,9 +778,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load) if (is_load) { switch (a->df) { - case 0: - gen_helper_msa_ld_b(tcg_env, wd, addr); - return true; case 1: gen_helper_msa_ld_h(tcg_env, wd, addr); return true; @@ -785,9 +790,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load) } } else { switch (a->df) { - case 0: - gen_helper_msa_st_b(tcg_env, wd, addr); - return true; case 1: gen_helper_msa_st_h(tcg_env, wd, addr); return true; @@ -800,6 +802,21 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load) } } + t16 = tcg_temp_new_i128(); + + mop = MO_128 | MO_LE; + mop |= mo_atom_df[a->df]; + + if (is_load) { + tcg_gen_qemu_ld_i128(t16, addr, ctx->mem_idx, mop); + tcg_gen_extr_i128_i64(d0, d1, t16); + } + + if (!is_load) { + tcg_gen_concat_i64_i128(t16, d0, d1); + tcg_gen_qemu_st_i128(t16, addr, ctx->mem_idx, mop); + } + return true; } -- 2.55.0
