Re: [PATCH v6 0/6] target/mips: Translate MSA vector load/store opcodes

[Richard Henderson]

On 10/29/26 10:13, Philippe Mathieu-Daudé wrote:

Missing review: 3 and 5

Since v5:
- Rebased
- Swap temporaries during store (rth)
- Bswap d0 and d1 in ST.D (rth)

Since v4:
- No algorithm change
- Split to ease review

Philippe Mathieu-Daudé (6):
   target/mips: Expand TRANS_DF_iv() macro for MSA Load/Store
   target/mips: Convert MSA LD/ST.B (Byte Vector)
   target/mips: Convert MSA LD/ST.H (Halfword Vector)
   target/mips: Convert MSA LD/ST.W (Word Vector)
   target/mips: Convert MSA LD/ST.D (Doubleword Vector)
   accel/tcg: Remove non-explicit endian cpu_ld/st*_data*() helpers

Reviewed-by: Richard Henderson <richard.hender...@linaro.org>

r~