[PATCH] D158688: [Driver,ARM,AArch64] Ignore -mbranch-protection= diagnostics for assembler input

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stuij added a comment.

LGTM. Thanks!


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[PATCH] D149444: [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections

[Ties Stuij via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
stuij marked an inline comment as done.
Closed by commit rG479955a42a71: [ARM] Allow codegen for Armv6m eXecute-Only 
(XO) sections (authored by stuij).

Changed prior to commit:
  https://reviews.llvm.org/D149444?vs=532684=548597#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149444/new/

https://reviews.llvm.org/D149444

Files:
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  clang/test/Driver/arm-execute-only.c


Index: clang/test/Driver/arm-execute-only.c
===
--- clang/test/Driver/arm-execute-only.c
+++ clang/test/Driver/arm-execute-only.c
@@ -1,19 +1,22 @@
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -fdriver-only -Werror --target=arm-arm-none-eabi \
+// RUN:   -march=armv6-m -mexecute-only %s 2>&1 | count 0
+
+// RUN: not %clang -### -c --target=arm-arm-none-eabi -march=armv6 
-mexecute-only %s 2>&1 |\
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
-// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for 
the thumbv6m sub-architecture
+// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for 
the armv6 sub-architecture
 
-// RUN: not %clang -target armv8m.main-eabi -mexecute-only -mno-movt %s 2>&1 \
+// RUN: not %clang -### --target=arm-arm-none-eabi -march=armv8-m.main 
-mexecute-only -mno-movt %s 2>&1 \
 // RUN:| FileCheck %s -check-prefix CHECK-EXECUTE-ONLY-NO-MOVT
 // CHECK-EXECUTE-ONLY-NO-MOVT: error: option '-mexecute-only' cannot be 
specified with '-mno-movt'
 
-// RUN: %clang -target armv7m-eabi -x assembler -mexecute-only %s -c -### 2>&1 
\
+// RUN: %clang -### --target=arm-arm-none-eabi -march=armv7-m -x assembler 
-mexecute-only %s -c -### 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-NO-EXECUTE-ONLY-ASM
 // CHECK-NO-EXECUTE-ONLY-ASM: warning: argument unused during compilation: 
'-mexecute-only'
 
 // -mpure-code flag for GCC compatibility
-// RUN: not %clang -c -target thumbv6m-eabi -mpure-code %s 2>&1 | \
+// RUN: not %clang -### -c --target=arm-arm-none-eabi -march=armv6 -mpure-code 
%s 2>&1 | \
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
 
-// RUN: not %clang -target armv8m.main-eabi -mpure-code -mno-movt %s 2>&1 \
+// RUN: not %clang -### --target=arm-arm-none-eabi -march=armv8-m.main 
-mpure-code -mno-movt %s 2>&1 \
 // RUN:| FileCheck %s -check-prefix CHECK-PURE-CODE-NO-MOVT
 // CHECK-PURE-CODE-NO-MOVT: error: option '-mpure-code' cannot be specified 
with '-mno-movt'
Index: clang/lib/Driver/ToolChains/Arch/ARM.cpp
===
--- clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -844,7 +844,8 @@
 if (Arg *A = Args.getLastArg(options::OPT_mexecute_only, 
options::OPT_mno_execute_only)) {
   if (A->getOption().matches(options::OPT_mexecute_only)) {
 if (getARMSubArchVersionNumber(Triple) < 7 &&
-llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2)
+llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2 &&
+llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6M)
   D.Diag(diag::err_target_unsupported_execute_only) << 
Triple.getArchName();
 else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
   D.Diag(diag::err_opt_not_valid_with_opt)


Index: clang/test/Driver/arm-execute-only.c
===
--- clang/test/Driver/arm-execute-only.c
+++ clang/test/Driver/arm-execute-only.c
@@ -1,19 +1,22 @@
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -fdriver-only -Werror --target=arm-arm-none-eabi \
+// RUN:   -march=armv6-m -mexecute-only %s 2>&1 | count 0
+
+// RUN: not %clang -### -c --target=arm-arm-none-eabi -march=armv6 -mexecute-only %s 2>&1 |\
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
-// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for the thumbv6m sub-architecture
+// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for the armv6 sub-architecture
 
-// RUN: not %clang -target armv8m.main-eabi -mexecute-only -mno-movt %s 2>&1 \
+// RUN: not %clang -### --target=arm-arm-none-eabi -march=armv8-m.main -mexecute-only -mno-movt %s 2>&1 \
 // RUN:| FileCheck %s -check-prefix CHECK-EXECUTE-ONLY-NO-MOVT
 // CHECK-EXECUTE-ONLY-NO-MOVT: error: option '-mexecute-only' cannot be specified with '-mno-movt'
 
-// RUN: %clang -target armv7m-eabi -x assembler -mexecute-only %s -c -### 2>&1 \
+// RUN: %clang -### --target=arm-arm-none-eabi -march=armv7-m -x assembler -mexecute-only 

[PATCH] D149443: [ARM] add Thumb-1 8-bit movs/adds relocations to LLVM

[Ties Stuij via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdc49fbd2df7d: [ARM] add Thumb-1 8-bit movs/adds relocations 
to LLVM (authored by stuij).

Changed prior to commit:
  https://reviews.llvm.org/D149443?vs=533190=533630#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  llvm/include/llvm/BinaryFormat/ELFRelocs/ARM.def
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrThumb.td
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
  llvm/test/MC/ARM/negative-immediates-thumb1-fail.s
  llvm/test/MC/ARM/thumb-8-bit-relocs.s
  llvm/test/MC/ARM/thumb-diagnostics.s
  llvm/test/MC/ARM/thumb-fixups.s

Index: llvm/test/MC/ARM/thumb-fixups.s
===
--- /dev/null
+++ llvm/test/MC/ARM/thumb-fixups.s
@@ -0,0 +1,25 @@
+@ RUN: llvm-mc -triple armv6m-unknown-unknown %s --show-encoding -o - | \
+@ RUN:   FileCheck %s
+
+movs r3, :upper8_15:_foo
+adds r3, :upper0_7:_foo
+adds r3, :lower8_15:_foo
+adds r3, :lower0_7:_foo
+
+@ CHECK:  movsr3, :upper8_15:_foo @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
+@ CHECK-NEXT: addsr3, :upper0_7:_foo  @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_0_7
+@ CHECK-NEXT: addsr3, :lower8_15:_foo @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_lower_8_15
+@ CHECK-NEXT: addsr3, :lower0_7:_foo  @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_lower_0_7
+
+@ GNU syntax variants:
+movs r3, #:upper8_15:#_foo
+movs r3, #:upper8_15:_foo
+
+@ CHECK:  movsr3, :upper8_15:_foo @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
+@ CHECK-NEXT: movsr3, :upper8_15:_foo @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
Index: llvm/test/MC/ARM/thumb-diagnostics.s
===
--- llvm/test/MC/ARM/thumb-diagnostics.s
+++ llvm/test/MC/ARM/thumb-diagnostics.s
@@ -195,6 +195,34 @@
 @ CHECK-ERRORS: note: operand must be an immediate in the range [0,31]
 @ CHECK-ERRORS: note: too many operands for instruction
 
+@ Out of range immediates for MOVS/ADDS instruction.
+movs r3, #-1
+adds r3, #256
+@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
+@ CHECK-ERRORS-NEXT: movs r3, #-1
+@ CHECK-ERRORS-NEXT: ^
+@ CHECK-ERRORS: note: operand must be an immediate in the range [0,255] or a relocatable expression
+@ CHECK-ERRORS-NEXT: movs r3, #-1
+@ CHECK-ERRORS-NEXT:  ^
+@ CHECK-ERRORS: note: operand must be a register in range [r0, r7]
+@ CHECK-ERRORS-NEXT: movs r3, #-1
+@ CHECK-ERRORS-NEXT:  ^
+@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT: ^
+@ CHECK-ERRORS: note: instruction requires: thumb2
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT: ^
+@ CHECK-ERRORS: note: invalid operand for instruction
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT:  ^
+@ CHECK-ERRORS-NEXT: note: operand must be an immediate in the range [0,255] or a relocatable expression
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT:  ^
+@ CHECK-ERRORS-NEXT: note: operand must be a register in range [r0, r7]
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT:  ^
+
 @ Mismatched source/destination operands for MUL instruction.
 muls r1, r2, r3
 @ CHECK-ERRORS: error: destination register must match source register
Index: llvm/test/MC/ARM/thumb-8-bit-relocs.s
===
--- /dev/null
+++ llvm/test/MC/ARM/thumb-8-bit-relocs.s
@@ -0,0 +1,35 @@
+@ RUN: llvm-mc -triple thumbv6m-eabi -o - %s | FileCheck %s
+@ RUN: llvm-mc -triple thumbv6m-eabi -filetype obj -o - %s | llvm-readobj -r - \
+@ RUN:   | FileCheck -check-prefix CHECK-RELOCATIONS %s
+@ RUN: llvm-mc -triple thumbv7m-eabi -o - %s | FileCheck %s
+@ RUN: llvm-mc -triple thumbv7m-eabi -filetype obj -o - %s | llvm-readobj -r - \
+@ RUN:   | FileCheck -check-prefix CHECK-RELOCATIONS %s
+
+.syntax unified
+
+.type function,%function
+function:
+  bx lr
+

[PATCH] D149443: [ARM] add Thumb-1 8-bit movs/adds relocations to LLVM

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 533190.
stuij added a comment.

address review comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149443/new/

https://reviews.llvm.org/D149443

Files:
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/include/llvm/BinaryFormat/ELFRelocs/ARM.def
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrThumb.td
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
  llvm/test/MC/ARM/negative-immediates-thumb1-fail.s
  llvm/test/MC/ARM/thumb-8-bit-relocs.s
  llvm/test/MC/ARM/thumb-diagnostics.s
  llvm/test/MC/ARM/thumb-fixups.s

Index: llvm/test/MC/ARM/thumb-fixups.s
===
--- /dev/null
+++ llvm/test/MC/ARM/thumb-fixups.s
@@ -0,0 +1,25 @@
+@ RUN: llvm-mc -triple armv6m-unknown-unknown %s --show-encoding -o - | \
+@ RUN:   FileCheck %s
+
+movs r3, :upper8_15:_foo
+adds r3, :upper0_7:_foo
+adds r3, :lower8_15:_foo
+adds r3, :lower0_7:_foo
+
+@ CHECK:  movsr3, :upper8_15:_foo @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
+@ CHECK-NEXT: addsr3, :upper0_7:_foo  @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_0_7
+@ CHECK-NEXT: addsr3, :lower8_15:_foo @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_lower_8_15
+@ CHECK-NEXT: addsr3, :lower0_7:_foo  @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_lower_0_7
+
+@ GNU syntax variants:
+movs r3, #:upper8_15:#_foo
+movs r3, #:upper8_15:_foo
+
+@ CHECK:  movsr3, :upper8_15:_foo @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
+@ CHECK-NEXT: movsr3, :upper8_15:_foo @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
Index: llvm/test/MC/ARM/thumb-diagnostics.s
===
--- llvm/test/MC/ARM/thumb-diagnostics.s
+++ llvm/test/MC/ARM/thumb-diagnostics.s
@@ -195,6 +195,34 @@
 @ CHECK-ERRORS: note: operand must be an immediate in the range [0,31]
 @ CHECK-ERRORS: note: too many operands for instruction
 
+@ Out of range immediates for MOVS/ADDS instruction.
+movs r3, #-1
+adds r3, #256
+@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
+@ CHECK-ERRORS-NEXT: movs r3, #-1
+@ CHECK-ERRORS-NEXT: ^
+@ CHECK-ERRORS: note: operand must be an immediate in the range [0,255] or a relocatable expression
+@ CHECK-ERRORS-NEXT: movs r3, #-1
+@ CHECK-ERRORS-NEXT:  ^
+@ CHECK-ERRORS: note: operand must be a register in range [r0, r7]
+@ CHECK-ERRORS-NEXT: movs r3, #-1
+@ CHECK-ERRORS-NEXT:  ^
+@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT: ^
+@ CHECK-ERRORS: note: instruction requires: thumb2
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT: ^
+@ CHECK-ERRORS: note: invalid operand for instruction
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT:  ^
+@ CHECK-ERRORS-NEXT: note: operand must be an immediate in the range [0,255] or a relocatable expression
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT:  ^
+@ CHECK-ERRORS-NEXT: note: operand must be a register in range [r0, r7]
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT:  ^
+
 @ Mismatched source/destination operands for MUL instruction.
 muls r1, r2, r3
 @ CHECK-ERRORS: error: destination register must match source register
Index: llvm/test/MC/ARM/thumb-8-bit-relocs.s
===
--- /dev/null
+++ llvm/test/MC/ARM/thumb-8-bit-relocs.s
@@ -0,0 +1,35 @@
+@ RUN: llvm-mc -triple thumbv6m-eabi -o - %s | FileCheck %s
+@ RUN: llvm-mc -triple thumbv6m-eabi -filetype obj -o - %s | llvm-readobj -r - \
+@ RUN:   | FileCheck -check-prefix CHECK-RELOCATIONS %s
+@ RUN: llvm-mc -triple thumbv7m-eabi -o - %s | FileCheck %s
+@ RUN: llvm-mc -triple thumbv7m-eabi -filetype obj -o - %s | llvm-readobj -r - \
+@ RUN:   | FileCheck -check-prefix CHECK-RELOCATIONS %s
+
+.syntax unified
+
+.type function,%function
+function:
+  bx lr
+
+.global external
+.type external,%function
+
+.type test,%function
+test:
+  movs r3, :upper8_15:function
+  adds r3, :upper0_7:function
+  adds r3, :lower8_15:function
+  adds r3, 

[PATCH] D149444: [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections

[Ties Stuij via Phabricator via cfe-commits]

stuij marked an inline comment as done.
stuij added a comment.






Comment at: clang/test/Driver/arm-execute-only.c:1
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -### --target=thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN:   FileCheck -allow-empty --check-prefix CHECK-EXECUTE-ONLY %s

MaskRay wrote:
> stuij wrote:
> > MaskRay wrote:
> > > If you don't check -cc1 options with FileCheck, you can also replace 
> > > `-###` with `-fdriver-only -Werror` and drop two `-NOT:` patterns below. 
> > > You can play with some examples to see its effect:)
> > > 
> > > If the `clang -c -fdriver-only -Werror` command gives no output, you can 
> > > use `... 2>&1 | count 0`
> > Very useful info. Thanks for the tips!
> LGTM once the simplification is done (e.g. `clang -c -fdriver-only -Werror`)
yup, thanks for that. I was struggling to get rid of those NOTs.


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[PATCH] D149443: [ARM] add Thumb-1 8-bit movs/adds relocations to LLVM

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 532685.
stuij marked 3 inline comments as done.
stuij added a comment.

addressed review comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149443/new/

https://reviews.llvm.org/D149443

Files:
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/include/llvm/BinaryFormat/ELFRelocs/ARM.def
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrThumb.td
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
  llvm/test/MC/ARM/negative-immediates-thumb1-fail.s
  llvm/test/MC/ARM/thumb-8-bit-relocs.s
  llvm/test/MC/ARM/thumb-diagnostics.s
  llvm/test/MC/ARM/thumb-fixups.s

Index: llvm/test/MC/ARM/thumb-fixups.s
===
--- /dev/null
+++ llvm/test/MC/ARM/thumb-fixups.s
@@ -0,0 +1,25 @@
+@ RUN: llvm-mc -triple armv6m-unknown-unknown %s --show-encoding > %t
+@ RUN: FileCheck < %t %s
+
+movs r3, :upper8_15:_foo
+adds r3, :upper0_7:_foo
+adds r3, :lower8_15:_foo
+adds r3, :lower0_7:_foo
+
+@ CHECK: movsr3, :upper8_15:_foo @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
+@ CHECK-NEXT: addsr3, :upper0_7:_foo  @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_0_7
+@ CHECK-NEXT: addsr3, :lower8_15:_foo @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_lower_8_15
+@ CHECK-NEXT: addsr3, :lower0_7:_foo  @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_lower_0_7
+
+@ GNU syntax variants:
+movs r3, #:upper8_15:#_foo
+movs r3, #:upper8_15:_foo
+
+@ CHECK: movsr3, :upper8_15:_foo @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
+@ CHECK-NEXT: movsr3, :upper8_15:_foo @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
Index: llvm/test/MC/ARM/thumb-diagnostics.s
===
--- llvm/test/MC/ARM/thumb-diagnostics.s
+++ llvm/test/MC/ARM/thumb-diagnostics.s
@@ -195,6 +195,34 @@
 @ CHECK-ERRORS: note: operand must be an immediate in the range [0,31]
 @ CHECK-ERRORS: note: too many operands for instruction
 
+@ Out of range immediates for MOVS/ADDS instruction.
+movs r3, #-1
+adds r3, #256
+@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
+@ CHECK-ERRORS-NEXT: movs r3, #-1
+@ CHECK-ERRORS-NEXT: ^
+@ CHECK-ERRORS: note: operand must be an immediate in the range [0,255] or a relocatable expression
+@ CHECK-ERRORS-NEXT: movs r3, #-1
+@ CHECK-ERRORS-NEXT:  ^
+@ CHECK-ERRORS: note: operand must be a register in range [r0, r7]
+@ CHECK-ERRORS-NEXT: movs r3, #-1
+@ CHECK-ERRORS-NEXT:  ^
+@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT: ^
+@ CHECK-ERRORS: note: instruction requires: thumb2
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT: ^
+@ CHECK-ERRORS: note: invalid operand for instruction
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT:  ^
+@ CHECK-ERRORS-NEXT: note: operand must be an immediate in the range [0,255] or a relocatable expression
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT:  ^
+@ CHECK-ERRORS-NEXT: note: operand must be a register in range [r0, r7]
+@ CHECK-ERRORS-NEXT: adds r3, #256
+@ CHECK-ERRORS-NEXT:  ^
+
 @ Mismatched source/destination operands for MUL instruction.
 muls r1, r2, r3
 @ CHECK-ERRORS: error: destination register must match source register
Index: llvm/test/MC/ARM/thumb-8-bit-relocs.s
===
--- /dev/null
+++ llvm/test/MC/ARM/thumb-8-bit-relocs.s
@@ -0,0 +1,35 @@
+@ RUN: llvm-mc -triple thumbv6m-eabi -o - %s | FileCheck %s
+@ RUN: llvm-mc -triple thumbv6m-eabi -filetype obj -o - %s | llvm-readobj -r - \
+@ RUN:   | FileCheck -check-prefix CHECK-RELOCATIONS %s
+@ RUN: llvm-mc -triple thumbv7m-eabi -o - %s | FileCheck %s
+@ RUN: llvm-mc -triple thumbv7m-eabi -filetype obj -o - %s | llvm-readobj -r - \
+@ RUN:   | FileCheck -check-prefix CHECK-RELOCATIONS %s
+
+.syntax unified
+
+.type function,%function
+function:
+  bx lr
+
+.global external
+.type external,%function
+
+.type test,%function
+test:
+  movs r3, :upper8_15:function
+  adds r3, :upper0_7:function
+  adds r3, 

[PATCH] D149444: [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 532684.
stuij added a comment.

address review comments


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Files:
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  clang/test/Driver/arm-execute-only.c


Index: clang/test/Driver/arm-execute-only.c
===
--- clang/test/Driver/arm-execute-only.c
+++ clang/test/Driver/arm-execute-only.c
@@ -1,19 +1,22 @@
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -fdriver-only -Werror --target=arm-arm-none-eabi \
+// RUN:   -march=armv6-m -mexecute-only %s 2>&1 | count 0
+
+// RUN: %clang -### -c --target=arm-arm-none-eabi -march=armv6 -mexecute-only 
%s 2>&1 |\
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
-// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for 
the thumbv6m sub-architecture
+// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for 
the armv6 sub-architecture
 
-// RUN: not %clang -target armv8m.main-eabi -mexecute-only -mno-movt %s 2>&1 \
+// RUN: %clang -### --target=arm-arm-none-eabi -march=armv8-m.main 
-mexecute-only -mno-movt %s 2>&1 \
 // RUN:| FileCheck %s -check-prefix CHECK-EXECUTE-ONLY-NO-MOVT
 // CHECK-EXECUTE-ONLY-NO-MOVT: error: option '-mexecute-only' cannot be 
specified with '-mno-movt'
 
-// RUN: %clang -target armv7m-eabi -x assembler -mexecute-only %s -c -### 2>&1 
\
+// RUN: %clang -### --target=arm-arm-none-eabi -march=armv7-m -x assembler 
-mexecute-only %s -c -### 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-NO-EXECUTE-ONLY-ASM
 // CHECK-NO-EXECUTE-ONLY-ASM: warning: argument unused during compilation: 
'-mexecute-only'
 
 // -mpure-code flag for GCC compatibility
-// RUN: not %clang -c -target thumbv6m-eabi -mpure-code %s 2>&1 | \
+// RUN: %clang -### -c --target=arm-arm-none-eabi -march=armv6 -mpure-code %s 
2>&1 | \
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
 
-// RUN: not %clang -target armv8m.main-eabi -mpure-code -mno-movt %s 2>&1 \
+// RUN: %clang -### --target=arm-arm-none-eabi -march=armv8-m.main -mpure-code 
-mno-movt %s 2>&1 \
 // RUN:| FileCheck %s -check-prefix CHECK-PURE-CODE-NO-MOVT
 // CHECK-PURE-CODE-NO-MOVT: error: option '-mpure-code' cannot be specified 
with '-mno-movt'
Index: clang/lib/Driver/ToolChains/Arch/ARM.cpp
===
--- clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -824,7 +824,8 @@
 if (Arg *A = Args.getLastArg(options::OPT_mexecute_only, 
options::OPT_mno_execute_only)) {
   if (A->getOption().matches(options::OPT_mexecute_only)) {
 if (getARMSubArchVersionNumber(Triple) < 7 &&
-llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2)
+llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2 &&
+llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6M)
   D.Diag(diag::err_target_unsupported_execute_only) << 
Triple.getArchName();
 else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
   D.Diag(diag::err_opt_not_valid_with_opt)


Index: clang/test/Driver/arm-execute-only.c
===
--- clang/test/Driver/arm-execute-only.c
+++ clang/test/Driver/arm-execute-only.c
@@ -1,19 +1,22 @@
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -fdriver-only -Werror --target=arm-arm-none-eabi \
+// RUN:   -march=armv6-m -mexecute-only %s 2>&1 | count 0
+
+// RUN: %clang -### -c --target=arm-arm-none-eabi -march=armv6 -mexecute-only %s 2>&1 |\
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
-// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for the thumbv6m sub-architecture
+// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for the armv6 sub-architecture
 
-// RUN: not %clang -target armv8m.main-eabi -mexecute-only -mno-movt %s 2>&1 \
+// RUN: %clang -### --target=arm-arm-none-eabi -march=armv8-m.main -mexecute-only -mno-movt %s 2>&1 \
 // RUN:| FileCheck %s -check-prefix CHECK-EXECUTE-ONLY-NO-MOVT
 // CHECK-EXECUTE-ONLY-NO-MOVT: error: option '-mexecute-only' cannot be specified with '-mno-movt'
 
-// RUN: %clang -target armv7m-eabi -x assembler -mexecute-only %s -c -### 2>&1 \
+// RUN: %clang -### --target=arm-arm-none-eabi -march=armv7-m -x assembler -mexecute-only %s -c -### 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-NO-EXECUTE-ONLY-ASM
 // CHECK-NO-EXECUTE-ONLY-ASM: warning: argument unused during compilation: '-mexecute-only'
 
 // -mpure-code flag for GCC compatibility
-// RUN: not %clang -c -target thumbv6m-eabi -mpure-code %s 2>&1 | \
+// 

[PATCH] D149444: [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections

[Ties Stuij via Phabricator via cfe-commits]

stuij added a comment.

In D149444#4425134 , @stuij wrote:

> - Moved the backend parts of this patch to D149443 
> .

Wrong Phab review -^ It should be D152795 .


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[PATCH] D149443: [ARM] add Thumb-1 8-bit movs/adds relocations to LLVM

[Ties Stuij via Phabricator via cfe-commits]

stuij added a comment.

In D149443#4403186 , @john.brawn 
wrote:

> A few comments:
>
> - Please run clang-format on the patch (pre-merge is showing as failed due to 
> this)
> - We should have a test to check that we're emitting the right relocation 
> (probably something similar to test/MC/ARM/thumb-movwt-reloc.s)
> - There should be something in ARMAsmParser::validateInstruction to check 
> that the expression is valid, like we do for movw/movt, as currently you can 
> do `movs r0, :lower16:some_symbol` and it's accepted and results in a 16-bit 
> mov with a movw relocation.
> - Something weird is happening when I try to use these expressions in movs on 
> v7m. If I try to assemble `movs r0, :upper8_15:some_symbol` I get "error: 
> expected relocatable expression", and looking at the `llvm-mc --show-encoding 
> --show-inst-operands` it's selected movs.w instead of 16-bit mov for some 
> reason.

the recent changes should have addressed all of these




Comment at: llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp:498-505
+  case ARM::fixup_arm_thumb_upper_8_15:
+return (Value & 0xff00) >> 24;
+  case ARM::fixup_arm_thumb_upper_0_7:
+return (Value & 0x00ff) >> 16;
+  case ARM::fixup_arm_thumb_lower_8_15:
+return (Value & 0xff00) >> 8;
+  case ARM::fixup_arm_thumb_lower_0_7:

john.brawn wrote:
> The calculation here isn't correct when IsResolved is false. In that case 
> we're calculating the addend for a relocation, and the value of that will be 
> `Value&0xff` for all four of these fixups (movw/movt has similar behaviour). 
done


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[PATCH] D149443: [ARM] add Thumb-1 8-bit movs/adds relocations to LLVM

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 531792.
stuij marked 2 inline comments as done.
stuij added a comment.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

addressed review comments


Repository:
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Files:
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/include/llvm/BinaryFormat/ELFRelocs/ARM.def
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrThumb.td
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
  llvm/test/MC/ARM/negative-immediates-thumb1-fail.s
  llvm/test/MC/ARM/thumb-8-bit-relocs.s
  llvm/test/MC/ARM/thumb-fixups.s

Index: llvm/test/MC/ARM/thumb-fixups.s
===
--- /dev/null
+++ llvm/test/MC/ARM/thumb-fixups.s
@@ -0,0 +1,25 @@
+@ RUN: llvm-mc -triple armv6m-unknown-unknown %s --show-encoding > %t
+@ RUN: FileCheck < %t %s
+
+movs r3, :upper8_15:_foo
+adds r3, :upper0_7:_foo
+adds r3, :lower8_15:_foo
+adds r3, :lower0_7:_foo
+
+@ CHECK: movsr3, :upper8_15:_foo @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
+@ CHECK-NEXT: addsr3, :upper0_7:_foo  @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_0_7
+@ CHECK-NEXT: addsr3, :lower8_15:_foo @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_lower_8_15
+@ CHECK-NEXT: addsr3, :lower0_7:_foo  @ encoding: [A,0x33]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_lower_0_7
+
+@ GNU syntax variants:
+movs r3, #:upper8_15:#_foo
+movs r3, #:upper8_15:_foo
+
+@ CHECK: movsr3, :upper8_15:_foo @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
+@ CHECK-NEXT: movsr3, :upper8_15:_foo @ encoding: [A,0x23]
+@ CHECK-NEXT: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_upper_8_15
Index: llvm/test/MC/ARM/thumb-8-bit-relocs.s
===
--- /dev/null
+++ llvm/test/MC/ARM/thumb-8-bit-relocs.s
@@ -0,0 +1,35 @@
+@ RUN: llvm-mc -triple thumbv6m-eabi -filetype asm -o - %s | FileCheck %s
+@ RUN: llvm-mc -triple thumbv6m-eabi -filetype obj -o - %s | llvm-readobj -r - \
+@ RUN:   | FileCheck -check-prefix CHECK-RELOCATIONS %s
+@ RUN: llvm-mc -triple thumbv7m-eabi -filetype asm -o - %s | FileCheck %s
+@ RUN: llvm-mc -triple thumbv7m-eabi -filetype obj -o - %s | llvm-readobj -r - \
+@ RUN:   | FileCheck -check-prefix CHECK-RELOCATIONS %s
+
+.syntax unified
+
+.type function,%function
+function:
+  bx lr
+
+.global external
+.type external,%function
+
+.type test,%function
+test:
+  movs r3, :upper8_15:function
+  adds r3, :upper0_7:function
+  adds r3, :lower8_15:function
+  adds r3, :lower0_7:function
+
+@ CHECK-LABEL: test:
+@ CHECK:  movs r3, :upper8_15:function
+@ CHECK:  adds r3, :upper0_7:function
+@ CHECK:  adds r3, :lower8_15:function
+@ CHECK:  adds r3, :lower0_7:function
+
+@ CHECK-RELOCATIONS: Relocations [
+@ CHECK-RELOCATIONS: 0x2 R_ARM_THM_ALU_ABS_G3 function
+@ CHECK-RELOCATIONS: 0x4 R_ARM_THM_ALU_ABS_G2_NC function
+@ CHECK-RELOCATIONS: 0x6 R_ARM_THM_ALU_ABS_G1_NC function
+@ CHECK-RELOCATIONS: 0x8 R_ARM_THM_ALU_ABS_G0_NC function
+@ CHECK-RELOCATIONS: ]
Index: llvm/test/MC/ARM/negative-immediates-thumb1-fail.s
===
--- llvm/test/MC/ARM/negative-immediates-thumb1-fail.s
+++ llvm/test/MC/ARM/negative-immediates-thumb1-fail.s
@@ -12,7 +12,7 @@
 ADDs r0, #0xFEFF
 # CHECK: error: invalid instruction, any one of the following would fix this:
 # CHECK-DAG: note: invalid operand for instruction
-# CHECK-DAG: note: operand must be an immediate in the range [0,255]
+# CHECK-DAG: note: operand must be an immediate in the range [0,255] or a relocatable expression
 
 SUBs r1, r0, #0xFFF5
 # CHECK: error: invalid instruction, any one of the following would fix this:
Index: llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
===
--- llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
+++ llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
@@ -17,8 +17,17 @@
 public:
   enum VariantKind {
 VK_ARM_None,
-VK_ARM_HI16,  // The R_ARM_MOVT_ABS relocation (:upper16: in the .s file)
-VK_ARM_LO16   // The R_ARM_MOVW_ABS_NC relocation (:lower16: in the .s file)
+VK_ARM_HI16, // The 

[PATCH] D149444: [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections

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stuij updated this revision to Diff 531787.
stuij added a comment.

- Moved the backend parts of this patch to D149443 
.
- Slightly tweaked the way we call the specific arch in the tests.


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Files:
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  clang/test/Driver/arm-execute-only.c


Index: clang/test/Driver/arm-execute-only.c
===
--- clang/test/Driver/arm-execute-only.c
+++ clang/test/Driver/arm-execute-only.c
@@ -1,19 +1,24 @@
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -### --target=arm-arm-none-eabi -march=armv6-m 
-mexecute-only %s 2>&1 | \
+// RUN:   FileCheck -allow-empty --check-prefix CHECK-EXECUTE-ONLY %s
+// CHECK-EXECUTE-ONLY-NOT: warning:
+// CHECK-EXECUTE-ONLY-NOT: error:
+
+// RUN: %clang -### -c --target=arm-arm-none-eabi -march=armv6 -mexecute-only 
%s 2>&1 |\
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
-// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for 
the thumbv6m sub-architecture
+// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for 
the armv6 sub-architecture
 
-// RUN: not %clang -target armv8m.main-eabi -mexecute-only -mno-movt %s 2>&1 \
+// RUN: %clang -### --target=arm-arm-none-eabi -march=armv8-m.main 
-mexecute-only -mno-movt %s 2>&1 \
 // RUN:| FileCheck %s -check-prefix CHECK-EXECUTE-ONLY-NO-MOVT
 // CHECK-EXECUTE-ONLY-NO-MOVT: error: option '-mexecute-only' cannot be 
specified with '-mno-movt'
 
-// RUN: %clang -target armv7m-eabi -x assembler -mexecute-only %s -c -### 2>&1 
\
+// RUN: %clang -### --target=arm-arm-none-eabi -march=armv7-m -x assembler 
-mexecute-only %s -c -### 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-NO-EXECUTE-ONLY-ASM
 // CHECK-NO-EXECUTE-ONLY-ASM: warning: argument unused during compilation: 
'-mexecute-only'
 
 // -mpure-code flag for GCC compatibility
-// RUN: not %clang -c -target thumbv6m-eabi -mpure-code %s 2>&1 | \
+// RUN: %clang -### -c --target=arm-arm-none-eabi -march=armv6 -mpure-code %s 
2>&1 | \
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
 
-// RUN: not %clang -target armv8m.main-eabi -mpure-code -mno-movt %s 2>&1 \
+// RUN: %clang -### --target=arm-arm-none-eabi -march=armv8-m.main -mpure-code 
-mno-movt %s 2>&1 \
 // RUN:| FileCheck %s -check-prefix CHECK-PURE-CODE-NO-MOVT
 // CHECK-PURE-CODE-NO-MOVT: error: option '-mpure-code' cannot be specified 
with '-mno-movt'
Index: clang/lib/Driver/ToolChains/Arch/ARM.cpp
===
--- clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -809,7 +809,8 @@
 if (Arg *A = Args.getLastArg(options::OPT_mexecute_only, 
options::OPT_mno_execute_only)) {
   if (A->getOption().matches(options::OPT_mexecute_only)) {
 if (getARMSubArchVersionNumber(Triple) < 7 &&
-llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2)
+llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2 &&
+llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6M)
   D.Diag(diag::err_target_unsupported_execute_only) << 
Triple.getArchName();
 else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
   D.Diag(diag::err_opt_not_valid_with_opt)


Index: clang/test/Driver/arm-execute-only.c
===
--- clang/test/Driver/arm-execute-only.c
+++ clang/test/Driver/arm-execute-only.c
@@ -1,19 +1,24 @@
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -### --target=arm-arm-none-eabi -march=armv6-m -mexecute-only %s 2>&1 | \
+// RUN:   FileCheck -allow-empty --check-prefix CHECK-EXECUTE-ONLY %s
+// CHECK-EXECUTE-ONLY-NOT: warning:
+// CHECK-EXECUTE-ONLY-NOT: error:
+
+// RUN: %clang -### -c --target=arm-arm-none-eabi -march=armv6 -mexecute-only %s 2>&1 |\
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
-// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for the thumbv6m sub-architecture
+// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for the armv6 sub-architecture
 
-// RUN: not %clang -target armv8m.main-eabi -mexecute-only -mno-movt %s 2>&1 \
+// RUN: %clang -### --target=arm-arm-none-eabi -march=armv8-m.main -mexecute-only -mno-movt %s 2>&1 \
 // RUN:| FileCheck %s -check-prefix CHECK-EXECUTE-ONLY-NO-MOVT
 // CHECK-EXECUTE-ONLY-NO-MOVT: error: option '-mexecute-only' cannot be specified with '-mno-movt'
 
-// RUN: %clang -target armv7m-eabi -x assembler -mexecute-only %s -c -### 2>&1 \
+// RUN: %clang -### 

[PATCH] D149444: [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections

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stuij added a comment.

In D149444#4415306 , @MaskRay wrote:

> Normally we implement the feature in llvm/ first, and the `clang/lib/Driver` 
> change should be the last patch.

Yes good point. I won't commit it yet. For this feature we're using Phab as a 
vehicle to swap patches, so we're reviewing these upstream as they become 
available.




Comment at: clang/test/Driver/arm-execute-only.c:1
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -### --target=thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN:   FileCheck -allow-empty --check-prefix CHECK-EXECUTE-ONLY %s

MaskRay wrote:
> If you don't check -cc1 options with FileCheck, you can also replace `-###` 
> with `-fdriver-only -Werror` and drop two `-NOT:` patterns below. You can 
> play with some examples to see its effect:)
> 
> If the `clang -c -fdriver-only -Werror` command gives no output, you can use 
> `... 2>&1 | count 0`
Very useful info. Thanks for the tips!


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[PATCH] D149444: [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 530505.
stuij marked 2 inline comments as done.
stuij added a comment.

addressed review comments


Repository:
  rG LLVM Github Monorepo

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Files:
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  clang/test/Driver/arm-execute-only.c
  llvm/lib/Target/ARM/ARMSubtarget.cpp


Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -187,10 +187,12 @@
   // Assert this for now to make the change obvious.
   assert(hasV6T2Ops() || !hasThumb2());
 
-  // Execute only support requires movt support
   if (genExecuteOnly()) {
-NoMovt = false;
-assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this 
target");
+// Execute only support for >= v8-M Baseline requires movt support
+if (hasV8MBaselineOps())
+  NoMovt = false;
+if (!hasV6MOps())
+  report_fatal_error("Cannot generate execute-only code for this target");
   }
 
   // Keep a pointer to static instruction cost data for the specified CPU.
Index: clang/test/Driver/arm-execute-only.c
===
--- clang/test/Driver/arm-execute-only.c
+++ clang/test/Driver/arm-execute-only.c
@@ -1,19 +1,24 @@
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -### --target=thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN:   FileCheck -allow-empty --check-prefix CHECK-EXECUTE-ONLY %s
+// CHECK-EXECUTE-ONLY-NOT: warning:
+// CHECK-EXECUTE-ONLY-NOT: error:
+
+// RUN: %clang -### -c --target=thumbv6-eabi -mexecute-only %s 2>&1 |\
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
-// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for 
the thumbv6m sub-architecture
+// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for 
the armv6 sub-architecture
 
-// RUN: not %clang -target armv8m.main-eabi -mexecute-only -mno-movt %s 2>&1 \
+// RUN: %clang -### --target=armv8m.main-eabi -mexecute-only -mno-movt %s 2>&1 
\
 // RUN:| FileCheck %s -check-prefix CHECK-EXECUTE-ONLY-NO-MOVT
 // CHECK-EXECUTE-ONLY-NO-MOVT: error: option '-mexecute-only' cannot be 
specified with '-mno-movt'
 
-// RUN: %clang -target armv7m-eabi -x assembler -mexecute-only %s -c -### 2>&1 
\
+// RUN: %clang -### --target=armv7m-eabi -x assembler -mexecute-only %s -c 
-### 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-NO-EXECUTE-ONLY-ASM
 // CHECK-NO-EXECUTE-ONLY-ASM: warning: argument unused during compilation: 
'-mexecute-only'
 
 // -mpure-code flag for GCC compatibility
-// RUN: not %clang -c -target thumbv6m-eabi -mpure-code %s 2>&1 | \
+// RUN: %clang -### -c --target=armv6-eabi -mpure-code %s 2>&1 | \
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
 
-// RUN: not %clang -target armv8m.main-eabi -mpure-code -mno-movt %s 2>&1 \
+// RUN: %clang -### -target armv8m.main-eabi -mpure-code -mno-movt %s 2>&1 \
 // RUN:| FileCheck %s -check-prefix CHECK-PURE-CODE-NO-MOVT
 // CHECK-PURE-CODE-NO-MOVT: error: option '-mpure-code' cannot be specified 
with '-mno-movt'
Index: clang/lib/Driver/ToolChains/Arch/ARM.cpp
===
--- clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -790,7 +790,8 @@
 if (Arg *A = Args.getLastArg(options::OPT_mexecute_only, 
options::OPT_mno_execute_only)) {
   if (A->getOption().matches(options::OPT_mexecute_only)) {
 if (getARMSubArchVersionNumber(Triple) < 7 &&
-llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2)
+llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2 &&
+llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6M)
   D.Diag(diag::err_target_unsupported_execute_only) << 
Triple.getArchName();
 else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
   D.Diag(diag::err_opt_not_valid_with_opt)


Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -187,10 +187,12 @@
   // Assert this for now to make the change obvious.
   assert(hasV6T2Ops() || !hasThumb2());
 
-  // Execute only support requires movt support
   if (genExecuteOnly()) {
-NoMovt = false;
-assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
+// Execute only support for >= v8-M Baseline requires movt support
+if (hasV8MBaselineOps())
+  NoMovt = false;
+if (!hasV6MOps())
+  report_fatal_error("Cannot generate execute-only code for this target");
   }
 
   // Keep a 

[PATCH] D149573: [Clang][C++23] Implement core language changes from P1467R9 extended floating-point types and standard names

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stuij added a comment.

This is going to be a very unhelpful comment. After looking through the 
changes, I don't have any comments to make, but I also don't feel comfortable 
to accept this revision as I don't feel to know enough about the front-end.


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[PATCH] D149444: [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections

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stuij added inline comments.



Comment at: llvm/lib/Target/ARM/ARMSubtarget.cpp:194
+  NoMovt = false;
+assert(hasV6MOps() && "Cannot generate execute-only code for this target");
   }

tschuett wrote:
> What happens in release mode? At the top you now claim that ARMV6M is 
> supported. Could hasV6MOps() silently return false?
This should really be caught by the frontend, but yes, I'm not sure why we use 
assert so often in this kind of code instead of unreachable. Changed.


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[PATCH] D149444: [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 525079.
stuij added a comment.

addressed review comment


Repository:
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Files:
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  clang/test/Driver/arm-execute-only.c
  llvm/lib/Target/ARM/ARMSubtarget.cpp


Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -187,10 +187,12 @@
   // Assert this for now to make the change obvious.
   assert(hasV6T2Ops() || !hasThumb2());
 
-  // Execute only support requires movt support
   if (genExecuteOnly()) {
-NoMovt = false;
-assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this 
target");
+// Execute only support for >= v8-M Baseline requires movt support
+if (hasV8MBaselineOps())
+  NoMovt = false;
+if (!hasV6MOps())
+  llvm_unreachable("Cannot generate execute-only code for this target");
   }
 
   // Keep a pointer to static instruction cost data for the specified CPU.
Index: clang/test/Driver/arm-execute-only.c
===
--- clang/test/Driver/arm-execute-only.c
+++ clang/test/Driver/arm-execute-only.c
@@ -1,6 +1,11 @@
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN:   FileCheck -allow-empty --check-prefix CHECK-THIS %s
+// CHECK-THIS-NOT: warning:
+// CHECK-THIS-NOT: error:
+
+// RUN: not %clang -c -target thumbv6-eabi -mexecute-only %s 2>&1 |\
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
-// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for 
the thumbv6m sub-architecture
+// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for 
the armv6 sub-architecture
 
 // RUN: not %clang -target armv8m.main-eabi -mexecute-only -mno-movt %s 2>&1 \
 // RUN:| FileCheck %s -check-prefix CHECK-EXECUTE-ONLY-NO-MOVT
@@ -11,7 +16,7 @@
 // CHECK-NO-EXECUTE-ONLY-ASM: warning: argument unused during compilation: 
'-mexecute-only'
 
 // -mpure-code flag for GCC compatibility
-// RUN: not %clang -c -target thumbv6m-eabi -mpure-code %s 2>&1 | \
+// RUN: not %clang -c -target armv6-eabi -mpure-code %s 2>&1 | \
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
 
 // RUN: not %clang -target armv8m.main-eabi -mpure-code -mno-movt %s 2>&1 \
Index: clang/lib/Driver/ToolChains/Arch/ARM.cpp
===
--- clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -790,7 +790,8 @@
 if (Arg *A = Args.getLastArg(options::OPT_mexecute_only, 
options::OPT_mno_execute_only)) {
   if (A->getOption().matches(options::OPT_mexecute_only)) {
 if (getARMSubArchVersionNumber(Triple) < 7 &&
-llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2)
+llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2 &&
+ llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6M)
   D.Diag(diag::err_target_unsupported_execute_only) << 
Triple.getArchName();
 else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
   D.Diag(diag::err_opt_not_valid_with_opt)


Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -187,10 +187,12 @@
   // Assert this for now to make the change obvious.
   assert(hasV6T2Ops() || !hasThumb2());
 
-  // Execute only support requires movt support
   if (genExecuteOnly()) {
-NoMovt = false;
-assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
+// Execute only support for >= v8-M Baseline requires movt support
+if (hasV8MBaselineOps())
+  NoMovt = false;
+if (!hasV6MOps())
+  llvm_unreachable("Cannot generate execute-only code for this target");
   }
 
   // Keep a pointer to static instruction cost data for the specified CPU.
Index: clang/test/Driver/arm-execute-only.c
===
--- clang/test/Driver/arm-execute-only.c
+++ clang/test/Driver/arm-execute-only.c
@@ -1,6 +1,11 @@
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN:   FileCheck -allow-empty --check-prefix CHECK-THIS %s
+// CHECK-THIS-NOT: warning:
+// CHECK-THIS-NOT: error:
+
+// RUN: not %clang -c -target thumbv6-eabi -mexecute-only %s 2>&1 |\
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
-// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: 

[PATCH] D149444: [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 524755.
stuij added a comment.

addressed review comments and updated tests


Repository:
  rG LLVM Github Monorepo

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Files:
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  clang/test/Driver/arm-execute-only.c
  llvm/lib/Target/ARM/ARMSubtarget.cpp


Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -187,10 +187,11 @@
   // Assert this for now to make the change obvious.
   assert(hasV6T2Ops() || !hasThumb2());
 
-  // Execute only support requires movt support
   if (genExecuteOnly()) {
-NoMovt = false;
-assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this 
target");
+// Execute only support for >= v8-M Baseline requires movt support
+if (hasV8MBaselineOps())
+  NoMovt = false;
+assert(hasV6MOps() && "Cannot generate execute-only code for this target");
   }
 
   // Keep a pointer to static instruction cost data for the specified CPU.
Index: clang/test/Driver/arm-execute-only.c
===
--- clang/test/Driver/arm-execute-only.c
+++ clang/test/Driver/arm-execute-only.c
@@ -1,6 +1,11 @@
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN:   FileCheck -allow-empty --check-prefix CHECK-THIS %s
+// CHECK-THIS-NOT: warning:
+// CHECK-THIS-NOT: error:
+
+// RUN: not %clang -c -target thumbv6-eabi -mexecute-only %s 2>&1 |\
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
-// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for 
the thumbv6m sub-architecture
+// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for 
the armv6 sub-architecture
 
 // RUN: not %clang -target armv8m.main-eabi -mexecute-only -mno-movt %s 2>&1 \
 // RUN:| FileCheck %s -check-prefix CHECK-EXECUTE-ONLY-NO-MOVT
@@ -11,7 +16,7 @@
 // CHECK-NO-EXECUTE-ONLY-ASM: warning: argument unused during compilation: 
'-mexecute-only'
 
 // -mpure-code flag for GCC compatibility
-// RUN: not %clang -c -target thumbv6m-eabi -mpure-code %s 2>&1 | \
+// RUN: not %clang -c -target armv6-eabi -mpure-code %s 2>&1 | \
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
 
 // RUN: not %clang -target armv8m.main-eabi -mpure-code -mno-movt %s 2>&1 \
Index: clang/lib/Driver/ToolChains/Arch/ARM.cpp
===
--- clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -790,7 +790,8 @@
 if (Arg *A = Args.getLastArg(options::OPT_mexecute_only, 
options::OPT_mno_execute_only)) {
   if (A->getOption().matches(options::OPT_mexecute_only)) {
 if (getARMSubArchVersionNumber(Triple) < 7 &&
-llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2)
+llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2 &&
+ llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6M)
   D.Diag(diag::err_target_unsupported_execute_only) << 
Triple.getArchName();
 else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
   D.Diag(diag::err_opt_not_valid_with_opt)


Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -187,10 +187,11 @@
   // Assert this for now to make the change obvious.
   assert(hasV6T2Ops() || !hasThumb2());
 
-  // Execute only support requires movt support
   if (genExecuteOnly()) {
-NoMovt = false;
-assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
+// Execute only support for >= v8-M Baseline requires movt support
+if (hasV8MBaselineOps())
+  NoMovt = false;
+assert(hasV6MOps() && "Cannot generate execute-only code for this target");
   }
 
   // Keep a pointer to static instruction cost data for the specified CPU.
Index: clang/test/Driver/arm-execute-only.c
===
--- clang/test/Driver/arm-execute-only.c
+++ clang/test/Driver/arm-execute-only.c
@@ -1,6 +1,11 @@
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN:   FileCheck -allow-empty --check-prefix CHECK-THIS %s
+// CHECK-THIS-NOT: warning:
+// CHECK-THIS-NOT: error:
+
+// RUN: not %clang -c -target thumbv6-eabi -mexecute-only %s 2>&1 |\
 // RUN:   FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
-// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not 

[PATCH] D149444: [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections

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stuij added inline comments.



Comment at: llvm/lib/Target/ARM/ARMSubtarget.cpp:434
   // range otherwise.
-  return !NoMovt && hasV8MBaselineOps() &&
+  return !NoMovt && hasV6MOps() &&
  (isTargetWindows() || !OptMinSize || genExecuteOnly());

simonwallis2 wrote:
> simonwallis2 wrote:
> > V6M does not have Movt.
> > At face value, this line looks wrong and leads to about 30 unit test fails.
> > 
> I clarify: there are no test fails with this patch on its own.
> The unit test fails I saw where when building this patch in conjunction with 
> related patch https://reviews.llvm.org/D149443
Correct, this shouldn't be here. Initially it looked like we were going to 
repurpose movt for v6m, but that should have been part of another patch. And 
now it looks like we'll handle v6m immediates separately. In any case I'll 
remove this.


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[PATCH] D149573: [Clang][C++23] Implement core language changes from P1467R9 extended floating-point types and standard names and adapt __bf16 to be arithmetic type

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stuij added a comment.

In D149573#4341323 , @codemzs wrote:

> @stuij, as you initially introduced `__bf16` as a storage-type, your review 
> on this adjustment would be greatly appreciated.

Sorry for the late reaction, was on holiday. Yes, I'll have a look. I've put it 
on my todo.


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[PATCH] D149573: [Clang][C++23] Implement core language changes from P1467R9 extended floating-point types and standard names and introduce Bfloat16 arithmetic type.

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stuij added a comment.

I made a comment on the RFC 

 to understand if we really need/want a new bfloat16 type.


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[PATCH] D150291: [Clang] Rename internal type identifier(s) for __bf16 to BF16Ty

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stuij accepted this revision.
stuij added a comment.

Regarding this particular change, we at Arm are happy with the name change. I 
saw BFloat16 instead of BF16 as tech debt that we didn't get round to fixing.

I do wonder if we need two bfloat implementations, but for that I'll leave a 
comment on D149573 .

BTW, unfortunately @lenary doesn't work at Arm anymore.


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[PATCH] D149444: [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections

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stuij created this revision.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
stuij requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

This patch moves the overall lower-bound arch restriction for Arm XO sections
from v8m to v6m. Actual implementation of code-gen for v6m will follow in
follow-up patches, which will include an implementation of relocations needed to
support this.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149444

Files:
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  llvm/lib/Target/ARM/ARMSubtarget.cpp


Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -191,7 +191,7 @@
   // Execute only support requires movt support
   if (genExecuteOnly()) {
 NoMovt = false;
-assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this 
target");
+assert(hasV6MOps() && "Cannot generate execute-only code for this target");
   }
 
   // Keep a pointer to static instruction cost data for the specified CPU.
@@ -431,7 +431,7 @@
   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
   // immediates as it is inherently position independent, and may be out of
   // range otherwise.
-  return !NoMovt && hasV8MBaselineOps() &&
+  return !NoMovt && hasV6MOps() &&
  (isTargetWindows() || !OptMinSize || genExecuteOnly());
 }
 
Index: clang/lib/Driver/ToolChains/Arch/ARM.cpp
===
--- clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -779,7 +779,8 @@
 if (Arg *A = Args.getLastArg(options::OPT_mexecute_only, 
options::OPT_mno_execute_only)) {
   if (A->getOption().matches(options::OPT_mexecute_only)) {
 if (getARMSubArchVersionNumber(Triple) < 7 &&
-llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2)
+llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6T2 &&
+ llvm::ARM::parseArch(Triple.getArchName()) != 
llvm::ARM::ArchKind::ARMV6M)
   D.Diag(diag::err_target_unsupported_execute_only) << 
Triple.getArchName();
 else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
   D.Diag(diag::err_opt_not_valid_with_opt)


Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -191,7 +191,7 @@
   // Execute only support requires movt support
   if (genExecuteOnly()) {
 NoMovt = false;
-assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
+assert(hasV6MOps() && "Cannot generate execute-only code for this target");
   }
 
   // Keep a pointer to static instruction cost data for the specified CPU.
@@ -431,7 +431,7 @@
   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
   // immediates as it is inherently position independent, and may be out of
   // range otherwise.
-  return !NoMovt && hasV8MBaselineOps() &&
+  return !NoMovt && hasV6MOps() &&
  (isTargetWindows() || !OptMinSize || genExecuteOnly());
 }
 
Index: clang/lib/Driver/ToolChains/Arch/ARM.cpp
===
--- clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -779,7 +779,8 @@
 if (Arg *A = Args.getLastArg(options::OPT_mexecute_only, options::OPT_mno_execute_only)) {
   if (A->getOption().matches(options::OPT_mexecute_only)) {
 if (getARMSubArchVersionNumber(Triple) < 7 &&
-llvm::ARM::parseArch(Triple.getArchName()) != llvm::ARM::ArchKind::ARMV6T2)
+llvm::ARM::parseArch(Triple.getArchName()) != llvm::ARM::ArchKind::ARMV6T2 &&
+ llvm::ARM::parseArch(Triple.getArchName()) != llvm::ARM::ArchKind::ARMV6M)
   D.Diag(diag::err_target_unsupported_execute_only) << Triple.getArchName();
 else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
   D.Diag(diag::err_opt_not_valid_with_opt)
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[PATCH] D136919: [X86][RFC] Change mangle name of __bf16 from u6__bf16 to DF16b

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stuij added a comment.

FWIW, at Arm we decided to keep the old name mangling to minimise friction with 
existing code/libraries, but allow more operations with this same 
name-mangling. We also discussed with Red Hat and they were ok with this.


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[PATCH] D76062: [PATCH] [ARM] ARMv8.6-a command-line + BFloat16 Asm Support

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Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:52
+  AArch64::AEK_RDM  | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+  AArch64::AEK_SM4  | AArch64::AEK_SHA3 | AArch64::AEK_BF16|
+  AArch64::AEK_SHA2 | AArch64::AEK_AES  | AArch64::AEK_I8MM))

ab wrote:
> stuij wrote:
> > SjoerdMeijer wrote:
> > > just double checking (because I can't remember): BF16 is a mandatory 
> > > extension?
> > for 8.2 it isn't, for 8.6 it is
> Belated question: what's the rationale for replacing `AEK_CRYPTO` with 
> SM4+SHA3+SHA2(+AES)?  I'm not aware of the required crypto bits changing, but 
> maybe I missed something.  There's a related question around how we should 
> deal with crypto here in the first place (remove FK, remove the crypto 
> exts?), but that seems orthogonal to v8.6a+ vs. v8.5a- implying different 
> crypto extensions.
> 
> For context, this comes up in D134351 where specifying `V8_6A` would enable 
> SM4, which we don't support.
Belated (initial) answer: yes unfortunately our crypto story is a bit of a mess 
(mostly related to it mandatory yes or no). we have a catch-all ticket on our 
backlog to deal with crypto inconsistencies, which will hopefully be picked up 
soon.

I've added your point, and so again hopefully soon we can provide clarity and 
smooth things out.


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[PATCH] D139608: [Clang][NFC] Add default `getBFloat16Mangling` impl

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stuij added a comment.

I went back and forth on this for a bit. There's a review outstanding to change 
the mangling name for X86: https://reviews.llvm.org/D136919 to align with the 
C++23 std::bfloat16_t issue from above. I settled on preferring to be 
conservative, and not risk at some point accidentally opting an arch into a 
name that doesn't conform with their ABI.


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[PATCH] D138488: [AArch64][clang] implement 2022 General Data-Processing instructions

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This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
stuij marked an inline comment as done.
Closed by commit rGcb261e30fbb1: [AArch64][clang] implement 2022 General 
Data-Processing instructions (authored by stuij).

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Files:
  clang/test/Driver/aarch64-cssc.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SystemOperands.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
  llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
  llvm/test/MC/AArch64/CSSC/abs_32.s
  llvm/test/MC/AArch64/CSSC/abs_64.s
  llvm/test/MC/AArch64/CSSC/cnt_32.s
  llvm/test/MC/AArch64/CSSC/cnt_64.s
  llvm/test/MC/AArch64/CSSC/ctz_32.s
  llvm/test/MC/AArch64/CSSC/ctz_64.s
  llvm/test/MC/AArch64/CSSC/smax_32_imm.s
  llvm/test/MC/AArch64/CSSC/smax_32_reg.s
  llvm/test/MC/AArch64/CSSC/smax_64_imm.s
  llvm/test/MC/AArch64/CSSC/smax_64_reg.s
  llvm/test/MC/AArch64/CSSC/smin_32_imm.s
  llvm/test/MC/AArch64/CSSC/smin_32_reg.s
  llvm/test/MC/AArch64/CSSC/smin_64_imm.s
  llvm/test/MC/AArch64/CSSC/smin_64_reg.s
  llvm/test/MC/AArch64/CSSC/umax_32_imm.s
  llvm/test/MC/AArch64/CSSC/umax_32_reg.s
  llvm/test/MC/AArch64/CSSC/umax_64_imm.s
  llvm/test/MC/AArch64/CSSC/umax_64_reg.s
  llvm/test/MC/AArch64/CSSC/umin_32_imm.s
  llvm/test/MC/AArch64/CSSC/umin_32_reg.s
  llvm/test/MC/AArch64/CSSC/umin_64_imm.s
  llvm/test/MC/AArch64/CSSC/umin_64_reg.s
  llvm/test/MC/AArch64/armv8.9a-cssc.s
  llvm/test/MC/AArch64/rprfm.s
  llvm/test/MC/Disassembler/AArch64/armv8.9a-cssc.txt
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1606,7 +1606,7 @@
   AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
   AArch64::AEK_SME2,AArch64::AEK_HBC,  AArch64::AEK_MOPS,
   AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,   AArch64::AEK_SME2p1,
-  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16};
+  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC};
 
   std::vector Features;
 
@@ -1671,6 +1671,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+hbc"));
   EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
   EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+cssc"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/test/MC/Disassembler/AArch64/armv8.9a-cssc.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/AArch64/armv8.9a-cssc.txt
@@ -0,0 +1,72 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.4a < %s  | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.8a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.9a < %s  | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.3a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+
+[0x20,0x20,0xc0,0xda]
+# CHECK:   abs x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x20,0xc0,0x5a]
+# CHECK:   abs w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x1c,0xc0,0xda]
+# CHECK:   cnt x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x1c,0xc0,0x5a]
+# CHECK:   cnt w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x18,0xc0,0xda]
+# CHECK:   ctz x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x18,0xc0,0x5a]
+# CHECK:   ctz w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x41,0x60,0xc3,0x9a]
+# CHECK:   smaxx1, x2, x3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc0,0x91]
+# CHECK:   smaxx1, x2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x60,0xc3,0x1a]
+# CHECK:   smaxw1, w2, w3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding

[PATCH] D138488: [AArch64][clang] implement 2022 General Data-Processing instructions

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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:11698
+//---
+// 2022 Architecture Extensions: General Data Processing (FEAT_V94_DP)
+//---

tschuett wrote:
> FEAT_CSSC or FEAT_V94_DP?
Yes, should be FEAT_CSSC. Thanks!


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[PATCH] D138488: [AArch64][clang] implement 2022 General Data-Processing instructions

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stuij updated this revision to Diff 477156.
stuij marked an inline comment as done.
stuij added a comment.

renamed *v94-dp* to *cssc*


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Files:
  clang/test/Driver/aarch64-cssc.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SystemOperands.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
  llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
  llvm/test/MC/AArch64/CSSC/abs_32.s
  llvm/test/MC/AArch64/CSSC/abs_64.s
  llvm/test/MC/AArch64/CSSC/cnt_32.s
  llvm/test/MC/AArch64/CSSC/cnt_64.s
  llvm/test/MC/AArch64/CSSC/ctz_32.s
  llvm/test/MC/AArch64/CSSC/ctz_64.s
  llvm/test/MC/AArch64/CSSC/smax_32_imm.s
  llvm/test/MC/AArch64/CSSC/smax_32_reg.s
  llvm/test/MC/AArch64/CSSC/smax_64_imm.s
  llvm/test/MC/AArch64/CSSC/smax_64_reg.s
  llvm/test/MC/AArch64/CSSC/smin_32_imm.s
  llvm/test/MC/AArch64/CSSC/smin_32_reg.s
  llvm/test/MC/AArch64/CSSC/smin_64_imm.s
  llvm/test/MC/AArch64/CSSC/smin_64_reg.s
  llvm/test/MC/AArch64/CSSC/umax_32_imm.s
  llvm/test/MC/AArch64/CSSC/umax_32_reg.s
  llvm/test/MC/AArch64/CSSC/umax_64_imm.s
  llvm/test/MC/AArch64/CSSC/umax_64_reg.s
  llvm/test/MC/AArch64/CSSC/umin_32_imm.s
  llvm/test/MC/AArch64/CSSC/umin_32_reg.s
  llvm/test/MC/AArch64/CSSC/umin_64_imm.s
  llvm/test/MC/AArch64/CSSC/umin_64_reg.s
  llvm/test/MC/AArch64/armv8.9a-cssc.s
  llvm/test/MC/AArch64/rprfm.s
  llvm/test/MC/Disassembler/AArch64/armv8.9a-cssc.txt
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1606,7 +1606,7 @@
   AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
   AArch64::AEK_SME2,AArch64::AEK_HBC,  AArch64::AEK_MOPS,
   AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,   AArch64::AEK_SME2p1,
-  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16};
+  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC};
 
   std::vector Features;
 
@@ -1671,6 +1671,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+hbc"));
   EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
   EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+cssc"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/test/MC/Disassembler/AArch64/armv8.9a-cssc.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/AArch64/armv8.9a-cssc.txt
@@ -0,0 +1,72 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.4a < %s  | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.8a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.9a < %s  | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.3a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+
+[0x20,0x20,0xc0,0xda]
+# CHECK:   abs x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x20,0xc0,0x5a]
+# CHECK:   abs w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x1c,0xc0,0xda]
+# CHECK:   cnt x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x1c,0xc0,0x5a]
+# CHECK:   cnt w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x18,0xc0,0xda]
+# CHECK:   ctz x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x18,0xc0,0x5a]
+# CHECK:   ctz w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x41,0x60,0xc3,0x9a]
+# CHECK:   smaxx1, x2, x3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc0,0x91]
+# CHECK:   smaxx1, x2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x60,0xc3,0x1a]
+# CHECK:   smaxw1, w2, w3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc0,0x11]
+# CHECK:   smaxw1, w2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x68,0xc3,0x9a]
+# CHECK:   

[PATCH] D138488: [AArch64][clang] implement 2022 General Data-Processing instructions

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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:11725
+: BaseTwoOperandRegReg,
+  Sched<[]> {
+  let Inst{11} = isMin;

dmgreen wrote:
> stuij wrote:
> > dmgreen wrote:
> > > Can we make this WriteI, maybe. I think that would probably be the 
> > > closest sched class.
> > I'm assuming you meant WriteLD.
> That would be a Load I believe. There are the min/max instructions?  I think 
> "simple ALU instruction" should be the closest match, which would be WriteI
ah right, sorry misread your comment.


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stuij updated this revision to Diff 477146.
stuij added a comment.

addressed review comment


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Files:
  clang/test/Driver/aarch64-cssc.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SystemOperands.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
  llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
  llvm/test/MC/AArch64/CSSC/abs_32.s
  llvm/test/MC/AArch64/CSSC/abs_64.s
  llvm/test/MC/AArch64/CSSC/cnt_32.s
  llvm/test/MC/AArch64/CSSC/cnt_64.s
  llvm/test/MC/AArch64/CSSC/ctz_32.s
  llvm/test/MC/AArch64/CSSC/ctz_64.s
  llvm/test/MC/AArch64/CSSC/smax_32_imm.s
  llvm/test/MC/AArch64/CSSC/smax_32_reg.s
  llvm/test/MC/AArch64/CSSC/smax_64_imm.s
  llvm/test/MC/AArch64/CSSC/smax_64_reg.s
  llvm/test/MC/AArch64/CSSC/smin_32_imm.s
  llvm/test/MC/AArch64/CSSC/smin_32_reg.s
  llvm/test/MC/AArch64/CSSC/smin_64_imm.s
  llvm/test/MC/AArch64/CSSC/smin_64_reg.s
  llvm/test/MC/AArch64/CSSC/umax_32_imm.s
  llvm/test/MC/AArch64/CSSC/umax_32_reg.s
  llvm/test/MC/AArch64/CSSC/umax_64_imm.s
  llvm/test/MC/AArch64/CSSC/umax_64_reg.s
  llvm/test/MC/AArch64/CSSC/umin_32_imm.s
  llvm/test/MC/AArch64/CSSC/umin_32_reg.s
  llvm/test/MC/AArch64/CSSC/umin_64_imm.s
  llvm/test/MC/AArch64/CSSC/umin_64_reg.s
  llvm/test/MC/AArch64/armv8.9a-v94-dp.s
  llvm/test/MC/AArch64/rprfm.s
  llvm/test/MC/Disassembler/AArch64/armv8.9a-v94-dp.txt
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1606,7 +1606,7 @@
   AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
   AArch64::AEK_SME2,AArch64::AEK_HBC,  AArch64::AEK_MOPS,
   AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,   AArch64::AEK_SME2p1,
-  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16};
+  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC};
 
   std::vector Features;
 
@@ -1671,6 +1671,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+hbc"));
   EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
   EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+cssc"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/test/MC/Disassembler/AArch64/armv8.9a-v94-dp.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/AArch64/armv8.9a-v94-dp.txt
@@ -0,0 +1,72 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.4a < %s  | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.8a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.9a < %s  | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.3a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+
+[0x20,0x20,0xc0,0xda]
+# CHECK:   abs x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x20,0xc0,0x5a]
+# CHECK:   abs w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x1c,0xc0,0xda]
+# CHECK:   cnt x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x1c,0xc0,0x5a]
+# CHECK:   cnt w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x18,0xc0,0xda]
+# CHECK:   ctz x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x18,0xc0,0x5a]
+# CHECK:   ctz w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x41,0x60,0xc3,0x9a]
+# CHECK:   smaxx1, x2, x3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc0,0x91]
+# CHECK:   smaxx1, x2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x60,0xc3,0x1a]
+# CHECK:   smaxw1, w2, w3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc0,0x11]
+# CHECK:   smaxw1, w2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x68,0xc3,0x9a]
+# CHECK:   sminx1, x2, x3
+# NO-V94A-ERR: 

[PATCH] D138488: [AArch64][clang] implement 2022 General Data-Processing instructions

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stuij added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:11725
+: BaseTwoOperandRegReg,
+  Sched<[]> {
+  let Inst{11} = isMin;

dmgreen wrote:
> Can we make this WriteI, maybe. I think that would probably be the closest 
> sched class.
I'm assuming you meant WriteLD.


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[PATCH] D138488: [AArch64][clang] implement 2022 General Data-Processing instructions

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stuij updated this revision to Diff 477143.
stuij marked 6 inline comments as done.
stuij added a comment.

addressed review comments


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/test/Driver/aarch64-cssc.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SystemOperands.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
  llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
  llvm/test/MC/AArch64/CSSC/abs_32.s
  llvm/test/MC/AArch64/CSSC/abs_64.s
  llvm/test/MC/AArch64/CSSC/cnt_32.s
  llvm/test/MC/AArch64/CSSC/cnt_64.s
  llvm/test/MC/AArch64/CSSC/ctz_32.s
  llvm/test/MC/AArch64/CSSC/ctz_64.s
  llvm/test/MC/AArch64/CSSC/smax_32_imm.s
  llvm/test/MC/AArch64/CSSC/smax_32_reg.s
  llvm/test/MC/AArch64/CSSC/smax_64_imm.s
  llvm/test/MC/AArch64/CSSC/smax_64_reg.s
  llvm/test/MC/AArch64/CSSC/smin_32_imm.s
  llvm/test/MC/AArch64/CSSC/smin_32_reg.s
  llvm/test/MC/AArch64/CSSC/smin_64_imm.s
  llvm/test/MC/AArch64/CSSC/smin_64_reg.s
  llvm/test/MC/AArch64/CSSC/umax_32_imm.s
  llvm/test/MC/AArch64/CSSC/umax_32_reg.s
  llvm/test/MC/AArch64/CSSC/umax_64_imm.s
  llvm/test/MC/AArch64/CSSC/umax_64_reg.s
  llvm/test/MC/AArch64/CSSC/umin_32_imm.s
  llvm/test/MC/AArch64/CSSC/umin_32_reg.s
  llvm/test/MC/AArch64/CSSC/umin_64_imm.s
  llvm/test/MC/AArch64/CSSC/umin_64_reg.s
  llvm/test/MC/AArch64/armv8.9a-v94-dp.s
  llvm/test/MC/AArch64/rprfm.s
  llvm/test/MC/Disassembler/AArch64/armv8.9a-v94-dp.txt
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1606,7 +1606,7 @@
   AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
   AArch64::AEK_SME2,AArch64::AEK_HBC,  AArch64::AEK_MOPS,
   AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,   AArch64::AEK_SME2p1,
-  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16};
+  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC};
 
   std::vector Features;
 
@@ -1671,6 +1671,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+hbc"));
   EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
   EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+cssc"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/test/MC/Disassembler/AArch64/armv8.9a-v94-dp.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/AArch64/armv8.9a-v94-dp.txt
@@ -0,0 +1,72 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.4a < %s  | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.8a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.9a < %s  | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.3a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+
+[0x20,0x20,0xc0,0xda]
+# CHECK:   abs x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x20,0xc0,0x5a]
+# CHECK:   abs w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x1c,0xc0,0xda]
+# CHECK:   cnt x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x1c,0xc0,0x5a]
+# CHECK:   cnt w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x18,0xc0,0xda]
+# CHECK:   ctz x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x18,0xc0,0x5a]
+# CHECK:   ctz w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x41,0x60,0xc3,0x9a]
+# CHECK:   smaxx1, x2, x3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc0,0x91]
+# CHECK:   smaxx1, x2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x60,0xc3,0x1a]
+# CHECK:   smaxw1, w2, w3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x0c,0xc0,0x11]
+# CHECK:   smaxw1, w2, #3
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x41,0x68,0xc3,0x9a]
+# 

[PATCH] D138488: [AArch64][clang] implement 2022 General Data-Processing instructions

[Ties Stuij via Phabricator via cfe-commits]

stuij created this revision.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
stuij requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch implements the 2022 Architecture General Data-Processing Instructions

They include:

Common Short Sequence Compression (CSSC) instructions

- scalar comparison instructions SMAX, SMIN, UMAX, UMIN (32/64 bits) with or 
without immediate
- ABS (absolute), CNT (count non-zero bits), CTZ (count trailing zeroes)
- command-line options for CSSC

Associated with these instructions in the documentation is the Range Prefetch
Memory (RPRFM) instruction, which signals to the memory system that data memory
accesses from a specified range of addresses are likely to occur in the near
future. The instruction lies in hint space, and is made unconditional.

Specs for the individual instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/

contributors to this patch:

- Cullen Rhodes
- Son Tuan Vu
- Mark Murray
- Tomas Matheson
- Sam Elliott
- Ties Stuij


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138488

Files:
  clang/test/Driver/aarch64-cssc.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SystemOperands.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
  llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
  llvm/test/MC/AArch64/CSSC/abs_32.s
  llvm/test/MC/AArch64/CSSC/abs_64.s
  llvm/test/MC/AArch64/CSSC/cnt_32.s
  llvm/test/MC/AArch64/CSSC/cnt_64.s
  llvm/test/MC/AArch64/CSSC/ctz_32.s
  llvm/test/MC/AArch64/CSSC/ctz_64.s
  llvm/test/MC/AArch64/CSSC/smax_32_imm.s
  llvm/test/MC/AArch64/CSSC/smax_32_reg.s
  llvm/test/MC/AArch64/CSSC/smax_64_imm.s
  llvm/test/MC/AArch64/CSSC/smax_64_reg.s
  llvm/test/MC/AArch64/CSSC/smin_32_imm.s
  llvm/test/MC/AArch64/CSSC/smin_32_reg.s
  llvm/test/MC/AArch64/CSSC/smin_64_imm.s
  llvm/test/MC/AArch64/CSSC/smin_64_reg.s
  llvm/test/MC/AArch64/CSSC/umax_32_imm.s
  llvm/test/MC/AArch64/CSSC/umax_32_reg.s
  llvm/test/MC/AArch64/CSSC/umax_64_imm.s
  llvm/test/MC/AArch64/CSSC/umax_64_reg.s
  llvm/test/MC/AArch64/CSSC/umin_32_imm.s
  llvm/test/MC/AArch64/CSSC/umin_32_reg.s
  llvm/test/MC/AArch64/CSSC/umin_64_imm.s
  llvm/test/MC/AArch64/CSSC/umin_64_reg.s
  llvm/test/MC/AArch64/armv9.4a-v94-dp.s
  llvm/test/MC/AArch64/rprfm.s
  llvm/test/MC/Disassembler/AArch64/armv9.4a-v94-dp.txt
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1606,7 +1606,7 @@
   AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
   AArch64::AEK_SME2,AArch64::AEK_HBC,  AArch64::AEK_MOPS,
   AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,   AArch64::AEK_SME2p1,
-  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16};
+  AArch64::AEK_B16B16,  AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC};
 
   std::vector Features;
 
@@ -1671,6 +1671,7 @@
   EXPECT_TRUE(llvm::is_contained(Features, "+hbc"));
   EXPECT_TRUE(llvm::is_contained(Features, "+mops"));
   EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+cssc"));
 
   // Assuming we listed every extension above, this should produce the same
   // result. (note that AEK_NONE doesn't have a name so it won't be in the
Index: llvm/test/MC/Disassembler/AArch64/armv9.4a-v94-dp.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/AArch64/armv9.4a-v94-dp.txt
@@ -0,0 +1,72 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.4a < %s  | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.8a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.9a < %s  | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.3a < %s 2>&1 | FileCheck --check-prefix=NO-V94A-ERR %s
+
+[0x20,0x20,0xc0,0xda]
+# CHECK:   abs x0, x1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x20,0xc0,0x5a]
+# CHECK:   abs w0, w1
+# NO-V94A-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x20,0x1c,0xc0,0xda]
+# CHECK:   cnt x0, x1

[PATCH] D138010: [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support

[Ties Stuij via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG983f63f7f0d1: [AArch64][ARM] add Armv8.9-a/Armv9.4-a 
identifier support (authored by stuij).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138010/new/

https://reviews.llvm.org/D138010

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-v89a.c
  clang/test/Driver/aarch64-v94a.c
  clang/test/Driver/arm-cortex-cpus-1.c
  clang/test/Preprocessor/arm-target-features.c
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Support/ARMTargetParserCommon.cpp
  llvm/lib/Support/Triple.cpp
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -32,10 +32,12 @@
 "armv8a",   "armv8l",  "armv8.1-a",  "armv8.1a","armv8.2-a",
 "armv8.2a", "armv8.3-a",   "armv8.3a",   "armv8.4-a",   "armv8.4a",
 "armv8.5-a","armv8.5a","armv8.6-a",  "armv8.6a","armv8.7-a",
-"armv8.7a", "armv8.8-a",   "armv8.8a",   "armv8-r", "armv8r",
-"armv8-m.base", "armv8m.base", "armv8-m.main",   "armv8m.main", "iwmmxt",
-"iwmmxt2",  "xscale",  "armv8.1-m.main", "armv9-a", "armv9",
-"armv9a",   "armv9.1-a",   "armv9.1a",   "armv9.2-a",   "armv9.2a",
+"armv8.7a", "armv8.8-a",   "armv8.8a",   "armv8.9-a",   "armv8.9a",
+"armv8-r",  "armv8r",  "armv8-m.base",   "armv8m.base", "armv8-m.main",
+"armv8m.main",  "iwmmxt",  "iwmmxt2","xscale",  "armv8.1-m.main",
+"armv9-a",  "armv9",   "armv9a", "armv9.1-a",   "armv9.1a",
+"armv9.2-a","armv9.2a","armv9.3-a",  "armv9.3a","armv9.4-a",
+"armv9.4a",
 };
 
 template 
@@ -510,6 +512,9 @@
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testARMArch("armv8.8-a", "generic", "v8.8a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(
+  testARMArch("armv8.9-a", "generic", "v8.9a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(
   testARMArch("armv9-a", "generic", "v9a",
   ARMBuildAttrs::CPUArch::v9_A));
@@ -522,6 +527,9 @@
   EXPECT_TRUE(
   testARMArch("armv9.3-a", "generic", "v9.3a",
   ARMBuildAttrs::CPUArch::v9_A));
+  EXPECT_TRUE(
+  testARMArch("armv9.4-a", "generic", "v9.4a",
+  ARMBuildAttrs::CPUArch::v9_A));
   EXPECT_TRUE(
   testARMArch("armv8-r", "cortex-r52", "v8r",
   ARMBuildAttrs::CPUArch::v8_R));
@@ -852,10 +860,12 @@
 case ARM::ArchKind::ARMV8_6A:
 case ARM::ArchKind::ARMV8_7A:
 case ARM::ArchKind::ARMV8_8A:
+case ARM::ArchKind::ARMV8_9A:
 case ARM::ArchKind::ARMV9A:
 case ARM::ArchKind::ARMV9_1A:
 case ARM::ArchKind::ARMV9_2A:
 case ARM::ArchKind::ARMV9_3A:
+case ARM::ArchKind::ARMV9_4A:
   EXPECT_EQ(ARM::ProfileKind::A, ARM::parseArchProfile(ARMArch[i]));
   break;
 default:
@@ -1422,12 +1432,18 @@
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv8.8-a", "generic", "v8.8a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testAArch64Arch("armv8.9-a", "generic", "v8.9a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv9-a", "generic", "v9a",
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv9.1-a", "generic", "v9.1a",
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv9.2-a", "generic", "v9.2a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testAArch64Arch("armv9.3-a", "generic", "v9.3a",
+  ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testAArch64Arch("armv9.4-a", "generic", "v9.4a",
+  ARMBuildAttrs::CPUArch::v8_A));
 }
 
 bool testAArch64Extension(StringRef CPUName, AArch64::ArchKind AK,
Index: llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
===
--- 

[PATCH] D138010: [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support

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Comment at: llvm/include/llvm/Support/ARMTargetParser.def:127
+  ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
+  ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM))
 ARM_ARCH("armv9-a", ARMV9A, "9-A", "v9a",

pratlucas wrote:
> stuij wrote:
> > tmatheson wrote:
> > > No ARM::AEK_SHA2 | ARM::AEK_AES? Or does 8.8 need updated?
> > Yes, I think 8.8 needs update, and some other arches as well.
> > 
> > In the A profile armarm, section A2.3, it is stated that from 8.2 SME(2) 
> > and EAS aren't by default included in the cryptographic extension as the 
> > Cryptographic Extension in an implementation is subject to export license 
> > controls. Inclusion of the extension can be either/or or none, so we should 
> > default to none.
> > 
> > I think this should be handled by  separate patch.
> The v8.9-a entry on AArch64TargetParser.def includes both `AEK_SHA2` and 
> `AEK_AES`. Can you also update it to make sure they are consistent?
Ai, I was mistaken. For v8 we have them enabled by default for historic 
reasons. For v9 we had the opportunity to disable them. So I will actually 
update v8.9 to add them here  :)


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[PATCH] D138010: [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support

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stuij updated this revision to Diff 475489.
stuij added a comment.

addressed review comments


Repository:
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Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-v89a.c
  clang/test/Driver/aarch64-v94a.c
  clang/test/Driver/arm-cortex-cpus-1.c
  clang/test/Preprocessor/arm-target-features.c
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Support/ARMTargetParserCommon.cpp
  llvm/lib/Support/Triple.cpp
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -32,10 +32,12 @@
 "armv8a",   "armv8l",  "armv8.1-a",  "armv8.1a","armv8.2-a",
 "armv8.2a", "armv8.3-a",   "armv8.3a",   "armv8.4-a",   "armv8.4a",
 "armv8.5-a","armv8.5a","armv8.6-a",  "armv8.6a","armv8.7-a",
-"armv8.7a", "armv8.8-a",   "armv8.8a",   "armv8-r", "armv8r",
-"armv8-m.base", "armv8m.base", "armv8-m.main",   "armv8m.main", "iwmmxt",
-"iwmmxt2",  "xscale",  "armv8.1-m.main", "armv9-a", "armv9",
-"armv9a",   "armv9.1-a",   "armv9.1a",   "armv9.2-a",   "armv9.2a",
+"armv8.7a", "armv8.8-a",   "armv8.8a",   "armv8.9-a",   "armv8.9a",
+"armv8-r",  "armv8r",  "armv8-m.base",   "armv8m.base", "armv8-m.main",
+"armv8m.main",  "iwmmxt",  "iwmmxt2","xscale",  "armv8.1-m.main",
+"armv9-a",  "armv9",   "armv9a", "armv9.1-a",   "armv9.1a",
+"armv9.2-a","armv9.2a","armv9.3-a",  "armv9.3a","armv9.4-a",
+"armv9.4a",
 };
 
 template 
@@ -510,6 +512,9 @@
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testARMArch("armv8.8-a", "generic", "v8.8a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(
+  testARMArch("armv8.9-a", "generic", "v8.9a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(
   testARMArch("armv9-a", "generic", "v9a",
   ARMBuildAttrs::CPUArch::v9_A));
@@ -522,6 +527,9 @@
   EXPECT_TRUE(
   testARMArch("armv9.3-a", "generic", "v9.3a",
   ARMBuildAttrs::CPUArch::v9_A));
+  EXPECT_TRUE(
+  testARMArch("armv9.4-a", "generic", "v9.4a",
+  ARMBuildAttrs::CPUArch::v9_A));
   EXPECT_TRUE(
   testARMArch("armv8-r", "cortex-r52", "v8r",
   ARMBuildAttrs::CPUArch::v8_R));
@@ -852,10 +860,12 @@
 case ARM::ArchKind::ARMV8_6A:
 case ARM::ArchKind::ARMV8_7A:
 case ARM::ArchKind::ARMV8_8A:
+case ARM::ArchKind::ARMV8_9A:
 case ARM::ArchKind::ARMV9A:
 case ARM::ArchKind::ARMV9_1A:
 case ARM::ArchKind::ARMV9_2A:
 case ARM::ArchKind::ARMV9_3A:
+case ARM::ArchKind::ARMV9_4A:
   EXPECT_EQ(ARM::ProfileKind::A, ARM::parseArchProfile(ARMArch[i]));
   break;
 default:
@@ -1422,12 +1432,18 @@
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv8.8-a", "generic", "v8.8a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testAArch64Arch("armv8.9-a", "generic", "v8.9a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv9-a", "generic", "v9a",
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv9.1-a", "generic", "v9.1a",
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv9.2-a", "generic", "v9.2a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testAArch64Arch("armv9.3-a", "generic", "v9.3a",
+  ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testAArch64Arch("armv9.4-a", "generic", "v9.4a",
+  ARMBuildAttrs::CPUArch::v8_A));
 }
 
 bool testAArch64Extension(StringRef CPUName, AArch64::ArchKind AK,
Index: llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
===
--- llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
+++ llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
@@ -890,10 +890,14 @@
   case ARM::ArchKind::ARMV8_4A:
   case 

[PATCH] D138010: [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support

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Comment at: llvm/include/llvm/Support/ARMTargetParser.def:127
+  ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
+  ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM))
 ARM_ARCH("armv9-a", ARMV9A, "9-A", "v9a",

tmatheson wrote:
> No ARM::AEK_SHA2 | ARM::AEK_AES? Or does 8.8 need updated?
Yes, I think 8.8 needs update, and some other arches as well.

In the A profile armarm, section A2.3, it is stated that from 8.2 SME(2) and 
EAS aren't by default included in the cryptographic extension as the 
Cryptographic Extension in an implementation is subject to export license 
controls. Inclusion of the extension can be either/or or none, so we should 
default to none.

I think this should be handled by  separate patch.


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[PATCH] D138010: [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support

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stuij updated this revision to Diff 475454.
stuij added a comment.

make work with recent TargetParser changes (D137924 
)


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Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-v89a.c
  clang/test/Driver/aarch64-v94a.c
  clang/test/Driver/arm-cortex-cpus-1.c
  clang/test/Preprocessor/arm-target-features.c
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Support/ARMTargetParserCommon.cpp
  llvm/lib/Support/Triple.cpp
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -32,10 +32,12 @@
 "armv8a",   "armv8l",  "armv8.1-a",  "armv8.1a","armv8.2-a",
 "armv8.2a", "armv8.3-a",   "armv8.3a",   "armv8.4-a",   "armv8.4a",
 "armv8.5-a","armv8.5a","armv8.6-a",  "armv8.6a","armv8.7-a",
-"armv8.7a", "armv8.8-a",   "armv8.8a",   "armv8-r", "armv8r",
-"armv8-m.base", "armv8m.base", "armv8-m.main",   "armv8m.main", "iwmmxt",
-"iwmmxt2",  "xscale",  "armv8.1-m.main", "armv9-a", "armv9",
-"armv9a",   "armv9.1-a",   "armv9.1a",   "armv9.2-a",   "armv9.2a",
+"armv8.7a", "armv8.8-a",   "armv8.8a",   "armv8.9-a",   "armv8.9a",
+"armv8-r",  "armv8r",  "armv8-m.base",   "armv8m.base", "armv8-m.main",
+"armv8m.main",  "iwmmxt",  "iwmmxt2","xscale",  "armv8.1-m.main",
+"armv9-a",  "armv9",   "armv9a", "armv9.1-a",   "armv9.1a",
+"armv9.2-a","armv9.2a","armv9.3-a",  "armv9.3a","armv9.4-a",
+"armv9.4a",
 };
 
 template 
@@ -510,6 +512,9 @@
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testARMArch("armv8.8-a", "generic", "v8.8a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(
+  testARMArch("armv8.9-a", "generic", "v8.9a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(
   testARMArch("armv9-a", "generic", "v9a",
   ARMBuildAttrs::CPUArch::v9_A));
@@ -522,6 +527,9 @@
   EXPECT_TRUE(
   testARMArch("armv9.3-a", "generic", "v9.3a",
   ARMBuildAttrs::CPUArch::v9_A));
+  EXPECT_TRUE(
+  testARMArch("armv9.4-a", "generic", "v9.4a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(
   testARMArch("armv8-r", "cortex-r52", "v8r",
   ARMBuildAttrs::CPUArch::v8_R));
@@ -852,10 +860,12 @@
 case ARM::ArchKind::ARMV8_6A:
 case ARM::ArchKind::ARMV8_7A:
 case ARM::ArchKind::ARMV8_8A:
+case ARM::ArchKind::ARMV8_9A:
 case ARM::ArchKind::ARMV9A:
 case ARM::ArchKind::ARMV9_1A:
 case ARM::ArchKind::ARMV9_2A:
 case ARM::ArchKind::ARMV9_3A:
+case ARM::ArchKind::ARMV9_4A:
   EXPECT_EQ(ARM::ProfileKind::A, ARM::parseArchProfile(ARMArch[i]));
   break;
 default:
@@ -1422,12 +1432,18 @@
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv8.8-a", "generic", "v8.8a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testAArch64Arch("armv8.9-a", "generic", "v8.9a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv9-a", "generic", "v9a",
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv9.1-a", "generic", "v9.1a",
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv9.2-a", "generic", "v9.2a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testAArch64Arch("armv9.3-a", "generic", "v9.3a",
+  ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testAArch64Arch("armv9.4-a", "generic", "v9.4a",
+  ARMBuildAttrs::CPUArch::v8_A));
 }
 
 bool testAArch64Extension(StringRef CPUName, AArch64::ArchKind AK,
Index: llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
===
--- llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
+++ llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
@@ 

[PATCH] D138010: [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support

[Ties Stuij via Phabricator via cfe-commits]

stuij created this revision.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
stuij requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

For both ARM and AArch64 add support for specifying -march=armv8.9a/armv9.4a to
clang. Add backend plumbing like target parser and predicate support.

For a summary of Amv8.9/Armv9.4 features, see:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022

For detailed information, consult the Arm Architecture Reference Manual for
A-profile architecture:
https://developer.arm.com/documentation/ddi0487/latest/

People who contributed to this patch:

- Keith Walker
- Ties Stuij


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138010

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-v89a.c
  clang/test/Driver/aarch64-v94a.c
  clang/test/Driver/arm-cortex-cpus-1.c
  clang/test/Preprocessor/arm-target-features.c
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Support/ARMTargetParser.cpp
  llvm/lib/Support/Triple.cpp
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -31,10 +31,12 @@
 "armv8a",   "armv8l",  "armv8.1-a",  "armv8.1a","armv8.2-a",
 "armv8.2a", "armv8.3-a",   "armv8.3a",   "armv8.4-a",   "armv8.4a",
 "armv8.5-a","armv8.5a","armv8.6-a",  "armv8.6a","armv8.7-a",
-"armv8.7a", "armv8.8-a",   "armv8.8a",   "armv8-r", "armv8r",
-"armv8-m.base", "armv8m.base", "armv8-m.main",   "armv8m.main", "iwmmxt",
-"iwmmxt2",  "xscale",  "armv8.1-m.main", "armv9-a", "armv9",
-"armv9a",   "armv9.1-a",   "armv9.1a",   "armv9.2-a",   "armv9.2a",
+"armv8.7a", "armv8.8-a",   "armv8.8a",   "armv8.9-a",   "armv8.9a",
+"armv8-r",  "armv8r",  "armv8-m.base",   "armv8m.base", "armv8-m.main",
+"armv8m.main",  "iwmmxt",  "iwmmxt2","xscale",  "armv8.1-m.main",
+"armv9-a",  "armv9",   "armv9a", "armv9.1-a",   "armv9.1a",
+"armv9.2-a","armv9.2a","armv9.3-a",  "armv9.3a","armv9.4-a",
+"armv9.4a",
 };
 
 template 
@@ -509,6 +511,9 @@
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testARMArch("armv8.8-a", "generic", "v8.8a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(
+  testARMArch("armv8.9-a", "generic", "v8.9a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(
   testARMArch("armv9-a", "generic", "v9a",
   ARMBuildAttrs::CPUArch::v9_A));
@@ -521,6 +526,9 @@
   EXPECT_TRUE(
   testARMArch("armv9.3-a", "generic", "v9.3a",
   ARMBuildAttrs::CPUArch::v9_A));
+  EXPECT_TRUE(
+  testARMArch("armv9.4-a", "generic", "v9.4a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(
   testARMArch("armv8-r", "cortex-r52", "v8r",
   ARMBuildAttrs::CPUArch::v8_R));
@@ -851,10 +859,12 @@
 case ARM::ArchKind::ARMV8_6A:
 case ARM::ArchKind::ARMV8_7A:
 case ARM::ArchKind::ARMV8_8A:
+case ARM::ArchKind::ARMV8_9A:
 case ARM::ArchKind::ARMV9A:
 case ARM::ArchKind::ARMV9_1A:
 case ARM::ArchKind::ARMV9_2A:
 case ARM::ArchKind::ARMV9_3A:
+case ARM::ArchKind::ARMV9_4A:
   EXPECT_EQ(ARM::ProfileKind::A, ARM::parseArchProfile(ARMArch[i]));
   break;
 default:
@@ -1429,12 +1439,18 @@
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv8.8-a", "generic", "v8.8a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testAArch64Arch("armv8.9-a", "generic", "v8.9a",
+  ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv9-a", "generic", "v9a",
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv9.1-a", "generic", "v9.1a",
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv9.2-a", "generic", "v9.2a",
   ARMBuildAttrs::CPUArch::v8_A));
+  EXPECT_TRUE(testAArch64Arch("armv9.3-a", 

[PATCH] D136919: [X86][RFC] Change mangle name of __bf16 from u6__bf16 to DF16b

[Ties Stuij via Phabricator via cfe-commits]

stuij added a comment.

As for Arm/AAch64, we're still assessing the amount of pain we'd cause with the 
name change, but we don't have an issue with letting go of storage-only.


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[PATCH] D135680: [clang][ARM] follow GCC behavior for defining __SOFTFP__

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This revision was automatically updated to reflect the committed changes.
stuij marked an inline comment as done.
Closed by commit rG95bbe9a19308: [clang][ARM] follow GCC behavior for defining 
__SOFTFP__ (authored by stuij).

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Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/test/Preprocessor/init-arm.c

Index: clang/test/Preprocessor/init-arm.c
===
--- clang/test/Preprocessor/init-arm.c
+++ clang/test/Preprocessor/init-arm.c
@@ -395,199 +395,593 @@
 // ARM-BE:#define __arm 1
 // ARM-BE:#define __arm__ 1
 
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-none-linux-gnueabi -target-feature +soft-float -target-feature +soft-float-abi < /dev/null | FileCheck -match-full-lines -check-prefix ARMEABISOFTFP %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-none-linux-gnueabi -target-feature +soft-float -target-feature +soft-float-abi < /dev/null | FileCheck -match-full-lines -check-prefix ARMEABISOFT %s
 //
-// ARMEABISOFTFP-NOT:#define _LP64
-// ARMEABISOFTFP:#define __APCS_32__ 1
-// ARMEABISOFTFP-NOT:#define __ARMEB__ 1
-// ARMEABISOFTFP:#define __ARMEL__ 1
-// ARMEABISOFTFP:#define __ARM_ARCH 4
-// ARMEABISOFTFP:#define __ARM_ARCH_4T__ 1
-// ARMEABISOFTFP-NOT:#define __ARM_BIG_ENDIAN 1
-// ARMEABISOFTFP:#define __ARM_EABI__ 1
-// ARMEABISOFTFP:#define __ARM_PCS 1
-// ARMEABISOFTFP-NOT:#define __ARM_PCS_VFP 1
-// ARMEABISOFTFP:#define __BIGGEST_ALIGNMENT__ 8
-// ARMEABISOFTFP:#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
-// ARMEABISOFTFP:#define __CHAR16_TYPE__ unsigned short
-// ARMEABISOFTFP:#define __CHAR32_TYPE__ unsigned int
-// ARMEABISOFTFP:#define __CHAR_BIT__ 8
-// ARMEABISOFTFP:#define __DBL_DENORM_MIN__ 4.9406564584124654e-324
-// ARMEABISOFTFP:#define __DBL_DIG__ 15
-// ARMEABISOFTFP:#define __DBL_EPSILON__ 2.2204460492503131e-16
-// ARMEABISOFTFP:#define __DBL_HAS_DENORM__ 1
-// ARMEABISOFTFP:#define __DBL_HAS_INFINITY__ 1
-// ARMEABISOFTFP:#define __DBL_HAS_QUIET_NAN__ 1
-// ARMEABISOFTFP:#define __DBL_MANT_DIG__ 53
-// ARMEABISOFTFP:#define __DBL_MAX_10_EXP__ 308
-// ARMEABISOFTFP:#define __DBL_MAX_EXP__ 1024
-// ARMEABISOFTFP:#define __DBL_MAX__ 1.7976931348623157e+308
-// ARMEABISOFTFP:#define __DBL_MIN_10_EXP__ (-307)
-// ARMEABISOFTFP:#define __DBL_MIN_EXP__ (-1021)
-// ARMEABISOFTFP:#define __DBL_MIN__ 2.2250738585072014e-308
-// ARMEABISOFTFP:#define __DECIMAL_DIG__ __LDBL_DECIMAL_DIG__
-// ARMEABISOFTFP:#define __FLT_DENORM_MIN__ 1.40129846e-45F
-// ARMEABISOFTFP:#define __FLT_DIG__ 6
-// ARMEABISOFTFP:#define __FLT_EPSILON__ 1.19209290e-7F
-// ARMEABISOFTFP:#define __FLT_HAS_DENORM__ 1
-// ARMEABISOFTFP:#define __FLT_HAS_INFINITY__ 1
-// ARMEABISOFTFP:#define __FLT_HAS_QUIET_NAN__ 1
-// ARMEABISOFTFP:#define __FLT_MANT_DIG__ 24
-// ARMEABISOFTFP:#define __FLT_MAX_10_EXP__ 38
-// ARMEABISOFTFP:#define __FLT_MAX_EXP__ 128
-// ARMEABISOFTFP:#define __FLT_MAX__ 3.40282347e+38F
-// ARMEABISOFTFP:#define __FLT_MIN_10_EXP__ (-37)
-// ARMEABISOFTFP:#define __FLT_MIN_EXP__ (-125)
-// ARMEABISOFTFP:#define __FLT_MIN__ 1.17549435e-38F
-// ARMEABISOFTFP:#define __FLT_RADIX__ 2
-// ARMEABISOFTFP:#define __INT16_C_SUFFIX__
-// ARMEABISOFTFP:#define __INT16_FMTd__ "hd"
-// ARMEABISOFTFP:#define __INT16_FMTi__ "hi"
-// ARMEABISOFTFP:#define __INT16_MAX__ 32767
-// ARMEABISOFTFP:#define __INT16_TYPE__ short
-// ARMEABISOFTFP:#define __INT32_C_SUFFIX__
-// ARMEABISOFTFP:#define __INT32_FMTd__ "d"
-// ARMEABISOFTFP:#define __INT32_FMTi__ "i"
-// ARMEABISOFTFP:#define __INT32_MAX__ 2147483647
-// ARMEABISOFTFP:#define __INT32_TYPE__ int
-// ARMEABISOFTFP:#define __INT64_C_SUFFIX__ LL
-// ARMEABISOFTFP:#define __INT64_FMTd__ "lld"
-// ARMEABISOFTFP:#define __INT64_FMTi__ "lli"
-// ARMEABISOFTFP:#define __INT64_MAX__ 9223372036854775807LL
-// ARMEABISOFTFP:#define __INT64_TYPE__ long long int
-// ARMEABISOFTFP:#define __INT8_C_SUFFIX__
-// ARMEABISOFTFP:#define __INT8_FMTd__ "hhd"
-// ARMEABISOFTFP:#define __INT8_FMTi__ "hhi"
-// ARMEABISOFTFP:#define __INT8_MAX__ 127
-// ARMEABISOFTFP:#define __INT8_TYPE__ signed char
-// ARMEABISOFTFP:#define __INTMAX_C_SUFFIX__ LL
-// ARMEABISOFTFP:#define __INTMAX_FMTd__ "lld"
-// ARMEABISOFTFP:#define __INTMAX_FMTi__ "lli"
-// ARMEABISOFTFP:#define __INTMAX_MAX__ 9223372036854775807LL
-// ARMEABISOFTFP:#define __INTMAX_TYPE__ long long int
-// ARMEABISOFTFP:#define __INTMAX_WIDTH__ 64
-// ARMEABISOFTFP:#define __INTPTR_FMTd__ "d"
-// ARMEABISOFTFP:#define __INTPTR_FMTi__ "i"
-// ARMEABISOFTFP:#define __INTPTR_MAX__ 2147483647
-// ARMEABISOFTFP:#define __INTPTR_TYPE__ int
-// ARMEABISOFTFP:#define __INTPTR_WIDTH__ 32
-// ARMEABISOFTFP:#define __INT_FAST16_FMTd__ "hd"
-// ARMEABISOFTFP:#define __INT_FAST16_FMTi__ "hi"
-// ARMEABISOFTFP:#define __INT_FAST16_MAX__ 32767
-// ARMEABISOFTFP:#define __INT_FAST16_TYPE__ short
-// ARMEABISOFTFP:#define 

[PATCH] D135680: [clang][ARM] follow GCC behavior for defining __SOFTFP__

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stuij marked an inline comment as done.
stuij added inline comments.



Comment at: clang/test/Preprocessor/init-arm.c:404
+//   is specified
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-none-linux-gnueabi 
-target-feature +soft-float -target-feature +soft-float-abi < /dev/null | 
FileCheck -match-full-lines -check-prefix ARMEABISOFTFP_NOFP %s
 //

pratlucas wrote:
> I believe this RUN line won't covered the new condition added to 
> `clang/lib/Basic/Targets/ARM.cpp` above, as it sets `+soft-float`.
> Can you add an extra test without that option enabled?
ah yes, thanks! added.


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[PATCH] D135680: [clang][ARM] follow GCC behavior for defining __SOFTFP__

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 468495.
stuij added a comment.

addressed review comment by adding test


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Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/test/Preprocessor/init-arm.c

Index: clang/test/Preprocessor/init-arm.c
===
--- clang/test/Preprocessor/init-arm.c
+++ clang/test/Preprocessor/init-arm.c
@@ -395,199 +395,593 @@
 // ARM-BE:#define __arm 1
 // ARM-BE:#define __arm__ 1
 
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-none-linux-gnueabi -target-feature +soft-float -target-feature +soft-float-abi < /dev/null | FileCheck -match-full-lines -check-prefix ARMEABISOFTFP %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-none-linux-gnueabi -target-feature +soft-float -target-feature +soft-float-abi < /dev/null | FileCheck -match-full-lines -check-prefix ARMEABISOFT %s
 //
-// ARMEABISOFTFP-NOT:#define _LP64
-// ARMEABISOFTFP:#define __APCS_32__ 1
-// ARMEABISOFTFP-NOT:#define __ARMEB__ 1
-// ARMEABISOFTFP:#define __ARMEL__ 1
-// ARMEABISOFTFP:#define __ARM_ARCH 4
-// ARMEABISOFTFP:#define __ARM_ARCH_4T__ 1
-// ARMEABISOFTFP-NOT:#define __ARM_BIG_ENDIAN 1
-// ARMEABISOFTFP:#define __ARM_EABI__ 1
-// ARMEABISOFTFP:#define __ARM_PCS 1
-// ARMEABISOFTFP-NOT:#define __ARM_PCS_VFP 1
-// ARMEABISOFTFP:#define __BIGGEST_ALIGNMENT__ 8
-// ARMEABISOFTFP:#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
-// ARMEABISOFTFP:#define __CHAR16_TYPE__ unsigned short
-// ARMEABISOFTFP:#define __CHAR32_TYPE__ unsigned int
-// ARMEABISOFTFP:#define __CHAR_BIT__ 8
-// ARMEABISOFTFP:#define __DBL_DENORM_MIN__ 4.9406564584124654e-324
-// ARMEABISOFTFP:#define __DBL_DIG__ 15
-// ARMEABISOFTFP:#define __DBL_EPSILON__ 2.2204460492503131e-16
-// ARMEABISOFTFP:#define __DBL_HAS_DENORM__ 1
-// ARMEABISOFTFP:#define __DBL_HAS_INFINITY__ 1
-// ARMEABISOFTFP:#define __DBL_HAS_QUIET_NAN__ 1
-// ARMEABISOFTFP:#define __DBL_MANT_DIG__ 53
-// ARMEABISOFTFP:#define __DBL_MAX_10_EXP__ 308
-// ARMEABISOFTFP:#define __DBL_MAX_EXP__ 1024
-// ARMEABISOFTFP:#define __DBL_MAX__ 1.7976931348623157e+308
-// ARMEABISOFTFP:#define __DBL_MIN_10_EXP__ (-307)
-// ARMEABISOFTFP:#define __DBL_MIN_EXP__ (-1021)
-// ARMEABISOFTFP:#define __DBL_MIN__ 2.2250738585072014e-308
-// ARMEABISOFTFP:#define __DECIMAL_DIG__ __LDBL_DECIMAL_DIG__
-// ARMEABISOFTFP:#define __FLT_DENORM_MIN__ 1.40129846e-45F
-// ARMEABISOFTFP:#define __FLT_DIG__ 6
-// ARMEABISOFTFP:#define __FLT_EPSILON__ 1.19209290e-7F
-// ARMEABISOFTFP:#define __FLT_HAS_DENORM__ 1
-// ARMEABISOFTFP:#define __FLT_HAS_INFINITY__ 1
-// ARMEABISOFTFP:#define __FLT_HAS_QUIET_NAN__ 1
-// ARMEABISOFTFP:#define __FLT_MANT_DIG__ 24
-// ARMEABISOFTFP:#define __FLT_MAX_10_EXP__ 38
-// ARMEABISOFTFP:#define __FLT_MAX_EXP__ 128
-// ARMEABISOFTFP:#define __FLT_MAX__ 3.40282347e+38F
-// ARMEABISOFTFP:#define __FLT_MIN_10_EXP__ (-37)
-// ARMEABISOFTFP:#define __FLT_MIN_EXP__ (-125)
-// ARMEABISOFTFP:#define __FLT_MIN__ 1.17549435e-38F
-// ARMEABISOFTFP:#define __FLT_RADIX__ 2
-// ARMEABISOFTFP:#define __INT16_C_SUFFIX__
-// ARMEABISOFTFP:#define __INT16_FMTd__ "hd"
-// ARMEABISOFTFP:#define __INT16_FMTi__ "hi"
-// ARMEABISOFTFP:#define __INT16_MAX__ 32767
-// ARMEABISOFTFP:#define __INT16_TYPE__ short
-// ARMEABISOFTFP:#define __INT32_C_SUFFIX__
-// ARMEABISOFTFP:#define __INT32_FMTd__ "d"
-// ARMEABISOFTFP:#define __INT32_FMTi__ "i"
-// ARMEABISOFTFP:#define __INT32_MAX__ 2147483647
-// ARMEABISOFTFP:#define __INT32_TYPE__ int
-// ARMEABISOFTFP:#define __INT64_C_SUFFIX__ LL
-// ARMEABISOFTFP:#define __INT64_FMTd__ "lld"
-// ARMEABISOFTFP:#define __INT64_FMTi__ "lli"
-// ARMEABISOFTFP:#define __INT64_MAX__ 9223372036854775807LL
-// ARMEABISOFTFP:#define __INT64_TYPE__ long long int
-// ARMEABISOFTFP:#define __INT8_C_SUFFIX__
-// ARMEABISOFTFP:#define __INT8_FMTd__ "hhd"
-// ARMEABISOFTFP:#define __INT8_FMTi__ "hhi"
-// ARMEABISOFTFP:#define __INT8_MAX__ 127
-// ARMEABISOFTFP:#define __INT8_TYPE__ signed char
-// ARMEABISOFTFP:#define __INTMAX_C_SUFFIX__ LL
-// ARMEABISOFTFP:#define __INTMAX_FMTd__ "lld"
-// ARMEABISOFTFP:#define __INTMAX_FMTi__ "lli"
-// ARMEABISOFTFP:#define __INTMAX_MAX__ 9223372036854775807LL
-// ARMEABISOFTFP:#define __INTMAX_TYPE__ long long int
-// ARMEABISOFTFP:#define __INTMAX_WIDTH__ 64
-// ARMEABISOFTFP:#define __INTPTR_FMTd__ "d"
-// ARMEABISOFTFP:#define __INTPTR_FMTi__ "i"
-// ARMEABISOFTFP:#define __INTPTR_MAX__ 2147483647
-// ARMEABISOFTFP:#define __INTPTR_TYPE__ int
-// ARMEABISOFTFP:#define __INTPTR_WIDTH__ 32
-// ARMEABISOFTFP:#define __INT_FAST16_FMTd__ "hd"
-// ARMEABISOFTFP:#define __INT_FAST16_FMTi__ "hi"
-// ARMEABISOFTFP:#define __INT_FAST16_MAX__ 32767
-// ARMEABISOFTFP:#define __INT_FAST16_TYPE__ short
-// ARMEABISOFTFP:#define __INT_FAST32_FMTd__ "d"
-// ARMEABISOFTFP:#define __INT_FAST32_FMTi__ "i"
-// ARMEABISOFTFP:#define __INT_FAST32_MAX__ 2147483647

[PATCH] D135680: [clang][ARM] follow GCC behavior for defining __SOFTFP__

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GCC behavior regarding defining __SOFTFP__ when (implicitly) specifying
-mfloat-abi=softfp:

- compile without (implicit) FP: define __SOFTFP__
- compile with (implicit) FP: don't define __SOFTFP__

Currently Clang doesn't define __SOFTFP__ when softfp is specified, either with
or without FP. This patch brings Clang in line with GCC behavior.


Repository:
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https://reviews.llvm.org/D135680

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/test/Preprocessor/init-arm.c

Index: clang/test/Preprocessor/init-arm.c
===
--- clang/test/Preprocessor/init-arm.c
+++ clang/test/Preprocessor/init-arm.c
@@ -395,199 +395,399 @@
 // ARM-BE:#define __arm 1
 // ARM-BE:#define __arm__ 1
 
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-none-linux-gnueabi -target-feature +soft-float -target-feature +soft-float-abi < /dev/null | FileCheck -match-full-lines -check-prefix ARMEABISOFTFP %s
+// explanation of difference between ARMEABISOFTFP_NOFP and ARMEABISOFTFP_FP
+// below:
+// - compile targets with no FPU should emit __SOFTFP__ 1 when +soft-float-abi
+//   is specified
+// - compile targets with FPU should not emit __SOFTFP__ 1 when +soft-float-abi
+//   is specified
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-none-linux-gnueabi -target-feature +soft-float -target-feature +soft-float-abi < /dev/null | FileCheck -match-full-lines -check-prefix ARMEABISOFTFP_NOFP %s
 //
-// ARMEABISOFTFP-NOT:#define _LP64
-// ARMEABISOFTFP:#define __APCS_32__ 1
-// ARMEABISOFTFP-NOT:#define __ARMEB__ 1
-// ARMEABISOFTFP:#define __ARMEL__ 1
-// ARMEABISOFTFP:#define __ARM_ARCH 4
-// ARMEABISOFTFP:#define __ARM_ARCH_4T__ 1
-// ARMEABISOFTFP-NOT:#define __ARM_BIG_ENDIAN 1
-// ARMEABISOFTFP:#define __ARM_EABI__ 1
-// ARMEABISOFTFP:#define __ARM_PCS 1
-// ARMEABISOFTFP-NOT:#define __ARM_PCS_VFP 1
-// ARMEABISOFTFP:#define __BIGGEST_ALIGNMENT__ 8
-// ARMEABISOFTFP:#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
-// ARMEABISOFTFP:#define __CHAR16_TYPE__ unsigned short
-// ARMEABISOFTFP:#define __CHAR32_TYPE__ unsigned int
-// ARMEABISOFTFP:#define __CHAR_BIT__ 8
-// ARMEABISOFTFP:#define __DBL_DENORM_MIN__ 4.9406564584124654e-324
-// ARMEABISOFTFP:#define __DBL_DIG__ 15
-// ARMEABISOFTFP:#define __DBL_EPSILON__ 2.2204460492503131e-16
-// ARMEABISOFTFP:#define __DBL_HAS_DENORM__ 1
-// ARMEABISOFTFP:#define __DBL_HAS_INFINITY__ 1
-// ARMEABISOFTFP:#define __DBL_HAS_QUIET_NAN__ 1
-// ARMEABISOFTFP:#define __DBL_MANT_DIG__ 53
-// ARMEABISOFTFP:#define __DBL_MAX_10_EXP__ 308
-// ARMEABISOFTFP:#define __DBL_MAX_EXP__ 1024
-// ARMEABISOFTFP:#define __DBL_MAX__ 1.7976931348623157e+308
-// ARMEABISOFTFP:#define __DBL_MIN_10_EXP__ (-307)
-// ARMEABISOFTFP:#define __DBL_MIN_EXP__ (-1021)
-// ARMEABISOFTFP:#define __DBL_MIN__ 2.2250738585072014e-308
-// ARMEABISOFTFP:#define __DECIMAL_DIG__ __LDBL_DECIMAL_DIG__
-// ARMEABISOFTFP:#define __FLT_DENORM_MIN__ 1.40129846e-45F
-// ARMEABISOFTFP:#define __FLT_DIG__ 6
-// ARMEABISOFTFP:#define __FLT_EPSILON__ 1.19209290e-7F
-// ARMEABISOFTFP:#define __FLT_HAS_DENORM__ 1
-// ARMEABISOFTFP:#define __FLT_HAS_INFINITY__ 1
-// ARMEABISOFTFP:#define __FLT_HAS_QUIET_NAN__ 1
-// ARMEABISOFTFP:#define __FLT_MANT_DIG__ 24
-// ARMEABISOFTFP:#define __FLT_MAX_10_EXP__ 38
-// ARMEABISOFTFP:#define __FLT_MAX_EXP__ 128
-// ARMEABISOFTFP:#define __FLT_MAX__ 3.40282347e+38F
-// ARMEABISOFTFP:#define __FLT_MIN_10_EXP__ (-37)
-// ARMEABISOFTFP:#define __FLT_MIN_EXP__ (-125)
-// ARMEABISOFTFP:#define __FLT_MIN__ 1.17549435e-38F
-// ARMEABISOFTFP:#define __FLT_RADIX__ 2
-// ARMEABISOFTFP:#define __INT16_C_SUFFIX__
-// ARMEABISOFTFP:#define __INT16_FMTd__ "hd"
-// ARMEABISOFTFP:#define __INT16_FMTi__ "hi"
-// ARMEABISOFTFP:#define __INT16_MAX__ 32767
-// ARMEABISOFTFP:#define __INT16_TYPE__ short
-// ARMEABISOFTFP:#define __INT32_C_SUFFIX__
-// ARMEABISOFTFP:#define __INT32_FMTd__ "d"
-// ARMEABISOFTFP:#define __INT32_FMTi__ "i"
-// ARMEABISOFTFP:#define __INT32_MAX__ 2147483647
-// ARMEABISOFTFP:#define __INT32_TYPE__ int
-// ARMEABISOFTFP:#define __INT64_C_SUFFIX__ LL
-// ARMEABISOFTFP:#define __INT64_FMTd__ "lld"
-// ARMEABISOFTFP:#define __INT64_FMTi__ "lli"
-// ARMEABISOFTFP:#define __INT64_MAX__ 9223372036854775807LL
-// ARMEABISOFTFP:#define __INT64_TYPE__ long long int
-// ARMEABISOFTFP:#define __INT8_C_SUFFIX__
-// ARMEABISOFTFP:#define __INT8_FMTd__ "hhd"
-// ARMEABISOFTFP:#define __INT8_FMTi__ "hhi"
-// ARMEABISOFTFP:#define __INT8_MAX__ 127
-// ARMEABISOFTFP:#define __INT8_TYPE__ signed char
-// ARMEABISOFTFP:#define __INTMAX_C_SUFFIX__ LL
-// ARMEABISOFTFP:#define __INTMAX_FMTd__ "lld"
-// ARMEABISOFTFP:#define __INTMAX_FMTi__ "lli"
-// ARMEABISOFTFP:#define __INTMAX_MAX__ 9223372036854775807LL
-// 

[PATCH] D131555: [Clang] Propagate const context info when emitting compound literal

[Ties Stuij via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
stuij marked an inline comment as done.
Closed by commit rG27cbfa7cc8cd: [Clang] Propagate const context info when 
emitting compound literal (authored by stuij).

Repository:
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  https://reviews.llvm.org/D131555/new/

https://reviews.llvm.org/D131555

Files:
  clang/lib/CodeGen/CGExprConstant.cpp
  clang/lib/CodeGen/ConstantEmitter.h
  clang/test/CodeGen/const-init.c


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s 
| FileCheck %s
+// setting strict FP behaviour in the run line below tests that the compiler
+// does the right thing for global compound literals (compoundliteral test)
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion 
-ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
@@ -181,3 +183,10 @@
 #pragma pack()
   // CHECK: @g31.a = internal global %struct.anon.2 { i16 23122, i32 
-12312731, i16 -312 }, align 4
 }
+
+// Clang should evaluate this in constant context, so floating point mode 
should
+// have no effect.
+// CHECK: @.compoundliteral = internal global [1 x float] [float 
0x3FB9A000], align 4
+struct { const float *floats; } compoundliteral = {
+  (float[1]) { 0.1, },
+};
Index: clang/lib/CodeGen/ConstantEmitter.h
===
--- clang/lib/CodeGen/ConstantEmitter.h
+++ clang/lib/CodeGen/ConstantEmitter.h
@@ -67,6 +67,9 @@
 return Abstract;
   }
 
+  bool isInConstantContext() const { return InConstantContext; }
+  void setInConstantContext(bool var) { InConstantContext = var; }
+
   /// Try to emit the initiaizer of the given declaration as an abstract
   /// constant.  If this succeeds, the emission must be finalized.
   llvm::Constant *tryEmitForInitializer(const VarDecl );
Index: clang/lib/CodeGen/CGExprConstant.cpp
===
--- clang/lib/CodeGen/CGExprConstant.cpp
+++ clang/lib/CodeGen/CGExprConstant.cpp
@@ -913,17 +913,16 @@
 // ConstExprEmitter
 
//===--===//
 
-static ConstantAddress tryEmitGlobalCompoundLiteral(CodeGenModule ,
-CodeGenFunction *CGF,
-  const CompoundLiteralExpr *E) {
+static ConstantAddress
+tryEmitGlobalCompoundLiteral(ConstantEmitter ,
+ const CompoundLiteralExpr *E) {
+  CodeGenModule  = emitter.CGM;
   CharUnits Align = CGM.getContext().getTypeAlignInChars(E->getType());
   if (llvm::GlobalVariable *Addr =
   CGM.getAddrOfConstantCompoundLiteralIfEmitted(E))
 return ConstantAddress(Addr, Addr->getValueType(), Align);
 
   LangAS addressSpace = E->getType().getAddressSpace();
-
-  ConstantEmitter emitter(CGM, CGF);
   llvm::Constant *C = emitter.tryEmitForInitializer(E->getInitializer(),
 addressSpace, 
E->getType());
   if (!C) {
@@ -1967,7 +1966,9 @@
 
 ConstantLValue
 ConstantLValueEmitter::VisitCompoundLiteralExpr(const CompoundLiteralExpr *E) {
-  return tryEmitGlobalCompoundLiteral(CGM, Emitter.CGF, E);
+  ConstantEmitter CompoundLiteralEmitter(CGM, Emitter.CGF);
+  CompoundLiteralEmitter.setInConstantContext(Emitter.isInConstantContext());
+  return tryEmitGlobalCompoundLiteral(CompoundLiteralEmitter, E);
 }
 
 ConstantLValue
@@ -2211,7 +2212,8 @@
 ConstantAddress
 CodeGenModule::GetAddrOfConstantCompoundLiteral(const CompoundLiteralExpr *E) {
   assert(E->isFileScope() && "not a file-scope compound literal expr");
-  return tryEmitGlobalCompoundLiteral(*this, nullptr, E);
+  ConstantEmitter emitter(*this);
+  return tryEmitGlobalCompoundLiteral(emitter, E);
 }
 
 llvm::Constant *


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s | FileCheck %s
+// setting strict FP behaviour in the run line below tests that the compiler
+// does the right thing for global compound literals (compoundliteral test)
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
@@ -181,3 +183,10 @@
 #pragma pack()
   // CHECK: 

[PATCH] D131555: [Clang] Propagate const context info when emitting compound literal

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Comment at: clang/test/CodeGen/const-init.c:2
+// setting strict FP behaviour in the run line below tests that the compiler
+// does the right thing for global compound literals (compoundliteral test)
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion 
-ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s

DavidSpickett wrote:
> Drive by comment, what is "the right thing" here? Without me having to git 
> blame this file if I'm looking at this months from now.
> 
> You could add a comment down next to the test like "clang should evaluate 
> this in a constant context, so floating point mode should have no effect". 
> Which is still a bit vague but better than "clang should not crash if we do 
> this".
> 
> Also are there any other floating point modes that have/had this same 
> problem? They should be tested too if so.
Yea, that does make the intent clearer. Added.


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addressed review comment


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Files:
  clang/lib/CodeGen/CGExprConstant.cpp
  clang/lib/CodeGen/ConstantEmitter.h
  clang/test/CodeGen/const-init.c


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s 
| FileCheck %s
+// setting strict FP behaviour in the run line below tests that the compiler
+// does the right thing for global compound literals (compoundliteral test)
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion 
-ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
@@ -181,3 +183,10 @@
 #pragma pack()
   // CHECK: @g31.a = internal global %struct.anon.2 { i16 23122, i32 
-12312731, i16 -312 }, align 4
 }
+
+// Clang should evaluate this in constant context, so floating point mode 
should
+// have no effect.
+// CHECK: @.compoundliteral = internal global [1 x float] [float 
0x3FB9A000], align 4
+struct { const float *floats; } compoundliteral = {
+  (float[1]) { 0.1, },
+};
Index: clang/lib/CodeGen/ConstantEmitter.h
===
--- clang/lib/CodeGen/ConstantEmitter.h
+++ clang/lib/CodeGen/ConstantEmitter.h
@@ -67,6 +67,9 @@
 return Abstract;
   }
 
+  bool isInConstantContext() const { return InConstantContext; }
+  void setInConstantContext(bool var) { InConstantContext = var; }
+
   /// Try to emit the initiaizer of the given declaration as an abstract
   /// constant.  If this succeeds, the emission must be finalized.
   llvm::Constant *tryEmitForInitializer(const VarDecl );
Index: clang/lib/CodeGen/CGExprConstant.cpp
===
--- clang/lib/CodeGen/CGExprConstant.cpp
+++ clang/lib/CodeGen/CGExprConstant.cpp
@@ -913,17 +913,16 @@
 // ConstExprEmitter
 
//===--===//
 
-static ConstantAddress tryEmitGlobalCompoundLiteral(CodeGenModule ,
-CodeGenFunction *CGF,
-  const CompoundLiteralExpr *E) {
+static ConstantAddress
+tryEmitGlobalCompoundLiteral(ConstantEmitter ,
+ const CompoundLiteralExpr *E) {
+  CodeGenModule  = emitter.CGM;
   CharUnits Align = CGM.getContext().getTypeAlignInChars(E->getType());
   if (llvm::GlobalVariable *Addr =
   CGM.getAddrOfConstantCompoundLiteralIfEmitted(E))
 return ConstantAddress(Addr, Addr->getValueType(), Align);
 
   LangAS addressSpace = E->getType().getAddressSpace();
-
-  ConstantEmitter emitter(CGM, CGF);
   llvm::Constant *C = emitter.tryEmitForInitializer(E->getInitializer(),
 addressSpace, 
E->getType());
   if (!C) {
@@ -1967,7 +1966,9 @@
 
 ConstantLValue
 ConstantLValueEmitter::VisitCompoundLiteralExpr(const CompoundLiteralExpr *E) {
-  return tryEmitGlobalCompoundLiteral(CGM, Emitter.CGF, E);
+  ConstantEmitter CompoundLiteralEmitter(CGM, Emitter.CGF);
+  CompoundLiteralEmitter.setInConstantContext(Emitter.isInConstantContext());
+  return tryEmitGlobalCompoundLiteral(CompoundLiteralEmitter, E);
 }
 
 ConstantLValue
@@ -2211,7 +2212,8 @@
 ConstantAddress
 CodeGenModule::GetAddrOfConstantCompoundLiteral(const CompoundLiteralExpr *E) {
   assert(E->isFileScope() && "not a file-scope compound literal expr");
-  return tryEmitGlobalCompoundLiteral(*this, nullptr, E);
+  ConstantEmitter emitter(*this);
+  return tryEmitGlobalCompoundLiteral(emitter, E);
 }
 
 llvm::Constant *


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s | FileCheck %s
+// setting strict FP behaviour in the run line below tests that the compiler
+// does the right thing for global compound literals (compoundliteral test)
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
@@ -181,3 +183,10 @@
 #pragma pack()
   // CHECK: @g31.a = internal global %struct.anon.2 { i16 23122, i32 -12312731, i16 -312 }, align 4
 }
+
+// Clang should evaluate this in constant 

[PATCH] D131555: [Clang] Propagate const context info when emitting compound literal

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stuij added inline comments.



Comment at: clang/lib/CodeGen/CGExprConstant.cpp:2217
   assert(E->isFileScope() && "not a file-scope compound literal expr");
-  return tryEmitGlobalCompoundLiteral(*this, nullptr, E);
+  ConstantEmitter emitter(*this, nullptr);
+  return tryEmitGlobalCompoundLiteral(emitter, E);

vhscampos wrote:
> vhscampos wrote:
> > This constructor has the second parameter optional anyway. I suggest you 
> > omit the nullptr here.
> To clarify, when I say optional, I mean it has a default value with is 
> already nullptr
done. thanks!



Comment at: clang/test/CodeGen/const-init.c:1
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s 
| FileCheck %s
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion 
-ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s
 

simon_tatham wrote:
> I think some kind of a comment would be useful saying what this option is 
> doing there -- at least, which one of the tests further down the file it's 
> supposed to apply to. Otherwise I could easily imagine someone throwing it 
> out again, and since the test would pass anyway, not noticing that it's no 
> longer testing what it's meant to test.
thanks, yes is done. I also added a check on generation of the float value.


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Files:
  clang/lib/CodeGen/CGExprConstant.cpp
  clang/lib/CodeGen/ConstantEmitter.h
  clang/test/CodeGen/const-init.c


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s 
| FileCheck %s
+// setting strict FP behaviour in the run line below tests that the compiler
+// does the right thing for global compound literals (compoundliteral test)
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion 
-ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
@@ -181,3 +183,8 @@
 #pragma pack()
   // CHECK: @g31.a = internal global %struct.anon.2 { i16 23122, i32 
-12312731, i16 -312 }, align 4
 }
+
+// CHECK: @.compoundliteral = internal global [1 x float] [float 
0x3FB9A000], align 4
+struct { const float *floats; } compoundliteral = {
+  (float[1]) { 0.1, },
+};
Index: clang/lib/CodeGen/ConstantEmitter.h
===
--- clang/lib/CodeGen/ConstantEmitter.h
+++ clang/lib/CodeGen/ConstantEmitter.h
@@ -67,6 +67,9 @@
 return Abstract;
   }
 
+  bool isInConstantContext() const { return InConstantContext; }
+  void setInConstantContext(bool var) { InConstantContext = var; }
+
   /// Try to emit the initiaizer of the given declaration as an abstract
   /// constant.  If this succeeds, the emission must be finalized.
   llvm::Constant *tryEmitForInitializer(const VarDecl );
Index: clang/lib/CodeGen/CGExprConstant.cpp
===
--- clang/lib/CodeGen/CGExprConstant.cpp
+++ clang/lib/CodeGen/CGExprConstant.cpp
@@ -913,17 +913,15 @@
 // ConstExprEmitter
 
//===--===//
 
-static ConstantAddress tryEmitGlobalCompoundLiteral(CodeGenModule ,
-CodeGenFunction *CGF,
+static ConstantAddress tryEmitGlobalCompoundLiteral(ConstantEmitter ,
   const CompoundLiteralExpr *E) {
+  CodeGenModule  = emitter.CGM;
   CharUnits Align = CGM.getContext().getTypeAlignInChars(E->getType());
   if (llvm::GlobalVariable *Addr =
   CGM.getAddrOfConstantCompoundLiteralIfEmitted(E))
 return ConstantAddress(Addr, Addr->getValueType(), Align);
 
   LangAS addressSpace = E->getType().getAddressSpace();
-
-  ConstantEmitter emitter(CGM, CGF);
   llvm::Constant *C = emitter.tryEmitForInitializer(E->getInitializer(),
 addressSpace, 
E->getType());
   if (!C) {
@@ -1970,7 +1968,9 @@
 
 ConstantLValue
 ConstantLValueEmitter::VisitCompoundLiteralExpr(const CompoundLiteralExpr *E) {
-  return tryEmitGlobalCompoundLiteral(CGM, Emitter.CGF, E);
+  ConstantEmitter CompoundLiteralEmitter(CGM, Emitter.CGF);
+  CompoundLiteralEmitter.setInConstantContext(Emitter.isInConstantContext());
+  return tryEmitGlobalCompoundLiteral(CompoundLiteralEmitter, E);
 }
 
 ConstantLValue
@@ -2214,7 +2214,8 @@
 ConstantAddress
 CodeGenModule::GetAddrOfConstantCompoundLiteral(const CompoundLiteralExpr *E) {
   assert(E->isFileScope() && "not a file-scope compound literal expr");
-  return tryEmitGlobalCompoundLiteral(*this, nullptr, E);
+  ConstantEmitter emitter(*this);
+  return tryEmitGlobalCompoundLiteral(emitter, E);
 }
 
 llvm::Constant *


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s | FileCheck %s
+// setting strict FP behaviour in the run line below tests that the compiler
+// does the right thing for global compound literals (compoundliteral test)
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
@@ -181,3 +183,8 @@
 #pragma pack()
   // CHECK: @g31.a = internal global %struct.anon.2 { i16 23122, i32 -12312731, i16 -312 }, align 4
 }
+
+// CHECK: @.compoundliteral = internal global [1 x float] [float 0x3FB9A000], align 4
+struct { const float *floats; } compoundliteral = {
+  (float[1]) { 0.1, },
+};
Index: 

[PATCH] D131555: [Clang] Propagate const context info when emitting compound literal

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stuij marked an inline comment as done.
stuij added a comment.

also added a comment above the runline. Initially thought it wouldn't be 
necessary as we're now doing a check, but I do agree that it's more clear to be 
specific about the cmdline arg.


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Files:
  clang/lib/CodeGen/CGExprConstant.cpp
  clang/lib/CodeGen/ConstantEmitter.h
  clang/test/CodeGen/const-init.c


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s 
| FileCheck %s
+// setting strict FP behaviour in the run line below tests that the compiler
+// does the right thing for global compound literals (compoundliteral test)
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion 
-ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
@@ -181,3 +183,8 @@
 #pragma pack()
   // CHECK: @g31.a = internal global %struct.anon.2 { i16 23122, i32 
-12312731, i16 -312 }, align 4
 }
+
+// CHECK: @.compoundliteral = internal global [1 x float] [float 
0x3FB9A000], align 4
+struct { const float *floats; } compoundliteral = {
+  (float[1]) { 0.1, },
+};
Index: clang/lib/CodeGen/ConstantEmitter.h
===
--- clang/lib/CodeGen/ConstantEmitter.h
+++ clang/lib/CodeGen/ConstantEmitter.h
@@ -67,6 +67,9 @@
 return Abstract;
   }
 
+  bool isInConstantContext() const { return InConstantContext; }
+  void setInConstantContext(bool var) { InConstantContext = var; }
+
   /// Try to emit the initiaizer of the given declaration as an abstract
   /// constant.  If this succeeds, the emission must be finalized.
   llvm::Constant *tryEmitForInitializer(const VarDecl );
Index: clang/lib/CodeGen/CGExprConstant.cpp
===
--- clang/lib/CodeGen/CGExprConstant.cpp
+++ clang/lib/CodeGen/CGExprConstant.cpp
@@ -913,17 +913,15 @@
 // ConstExprEmitter
 
//===--===//
 
-static ConstantAddress tryEmitGlobalCompoundLiteral(CodeGenModule ,
-CodeGenFunction *CGF,
+static ConstantAddress tryEmitGlobalCompoundLiteral(ConstantEmitter ,
   const CompoundLiteralExpr *E) {
+  CodeGenModule  = emitter.CGM;
   CharUnits Align = CGM.getContext().getTypeAlignInChars(E->getType());
   if (llvm::GlobalVariable *Addr =
   CGM.getAddrOfConstantCompoundLiteralIfEmitted(E))
 return ConstantAddress(Addr, Addr->getValueType(), Align);
 
   LangAS addressSpace = E->getType().getAddressSpace();
-
-  ConstantEmitter emitter(CGM, CGF);
   llvm::Constant *C = emitter.tryEmitForInitializer(E->getInitializer(),
 addressSpace, 
E->getType());
   if (!C) {
@@ -1970,7 +1968,9 @@
 
 ConstantLValue
 ConstantLValueEmitter::VisitCompoundLiteralExpr(const CompoundLiteralExpr *E) {
-  return tryEmitGlobalCompoundLiteral(CGM, Emitter.CGF, E);
+  ConstantEmitter CompoundLiteralEmitter(CGM, Emitter.CGF);
+  CompoundLiteralEmitter.setInConstantContext(Emitter.isInConstantContext());
+  return tryEmitGlobalCompoundLiteral(CompoundLiteralEmitter, E);
 }
 
 ConstantLValue
@@ -2214,7 +2214,8 @@
 ConstantAddress
 CodeGenModule::GetAddrOfConstantCompoundLiteral(const CompoundLiteralExpr *E) {
   assert(E->isFileScope() && "not a file-scope compound literal expr");
-  return tryEmitGlobalCompoundLiteral(*this, nullptr, E);
+  ConstantEmitter emitter(*this, nullptr);
+  return tryEmitGlobalCompoundLiteral(emitter, E);
 }
 
 llvm::Constant *


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s | FileCheck %s
+// setting strict FP behaviour in the run line below tests that the compiler
+// does the right thing for global compound literals (compoundliteral test)
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
@@ -181,3 +183,8 @@
 #pragma pack()
   // CHECK: @g31.a = internal global %struct.anon.2 { i16 23122, i32 -12312731, i16 -312 }, align 4
 }
+
+// 

[PATCH] D131555: [Clang] Propagate const context info when emitting compound literal

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stuij updated this revision to Diff 451781.
stuij added a comment.

addressed review comments


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Files:
  clang/lib/CodeGen/CGExprConstant.cpp
  clang/lib/CodeGen/ConstantEmitter.h
  clang/test/CodeGen/const-init.c


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s 
| FileCheck %s
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion 
-ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
@@ -181,3 +181,8 @@
 #pragma pack()
   // CHECK: @g31.a = internal global %struct.anon.2 { i16 23122, i32 
-12312731, i16 -312 }, align 4
 }
+
+// CHECK: @.compoundliteral = internal global [1 x float] [float 
0x3FB9A000], align 4
+struct { const float *floats; } compoundliteral = {
+  (float[1]) { 0.1, },
+};
Index: clang/lib/CodeGen/ConstantEmitter.h
===
--- clang/lib/CodeGen/ConstantEmitter.h
+++ clang/lib/CodeGen/ConstantEmitter.h
@@ -67,6 +67,9 @@
 return Abstract;
   }
 
+  bool isInConstantContext() const { return InConstantContext; }
+  void setInConstantContext(bool var) { InConstantContext = var; }
+
   /// Try to emit the initiaizer of the given declaration as an abstract
   /// constant.  If this succeeds, the emission must be finalized.
   llvm::Constant *tryEmitForInitializer(const VarDecl );
Index: clang/lib/CodeGen/CGExprConstant.cpp
===
--- clang/lib/CodeGen/CGExprConstant.cpp
+++ clang/lib/CodeGen/CGExprConstant.cpp
@@ -913,17 +913,15 @@
 // ConstExprEmitter
 
//===--===//
 
-static ConstantAddress tryEmitGlobalCompoundLiteral(CodeGenModule ,
-CodeGenFunction *CGF,
+static ConstantAddress tryEmitGlobalCompoundLiteral(ConstantEmitter ,
   const CompoundLiteralExpr *E) {
+  CodeGenModule  = emitter.CGM;
   CharUnits Align = CGM.getContext().getTypeAlignInChars(E->getType());
   if (llvm::GlobalVariable *Addr =
   CGM.getAddrOfConstantCompoundLiteralIfEmitted(E))
 return ConstantAddress(Addr, Addr->getValueType(), Align);
 
   LangAS addressSpace = E->getType().getAddressSpace();
-
-  ConstantEmitter emitter(CGM, CGF);
   llvm::Constant *C = emitter.tryEmitForInitializer(E->getInitializer(),
 addressSpace, 
E->getType());
   if (!C) {
@@ -1970,7 +1968,9 @@
 
 ConstantLValue
 ConstantLValueEmitter::VisitCompoundLiteralExpr(const CompoundLiteralExpr *E) {
-  return tryEmitGlobalCompoundLiteral(CGM, Emitter.CGF, E);
+  ConstantEmitter CompoundLiteralEmitter(CGM, Emitter.CGF);
+  CompoundLiteralEmitter.setInConstantContext(Emitter.isInConstantContext());
+  return tryEmitGlobalCompoundLiteral(CompoundLiteralEmitter, E);
 }
 
 ConstantLValue
@@ -2214,7 +2214,8 @@
 ConstantAddress
 CodeGenModule::GetAddrOfConstantCompoundLiteral(const CompoundLiteralExpr *E) {
   assert(E->isFileScope() && "not a file-scope compound literal expr");
-  return tryEmitGlobalCompoundLiteral(*this, nullptr, E);
+  ConstantEmitter emitter(*this, nullptr);
+  return tryEmitGlobalCompoundLiteral(emitter, E);
 }
 
 llvm::Constant *


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
@@ -181,3 +181,8 @@
 #pragma pack()
   // CHECK: @g31.a = internal global %struct.anon.2 { i16 23122, i32 -12312731, i16 -312 }, align 4
 }
+
+// CHECK: @.compoundliteral = internal global [1 x float] [float 0x3FB9A000], align 4
+struct { const float *floats; } compoundliteral = {
+  (float[1]) { 0.1, },
+};
Index: clang/lib/CodeGen/ConstantEmitter.h
===
--- clang/lib/CodeGen/ConstantEmitter.h
+++ clang/lib/CodeGen/ConstantEmitter.h
@@ -67,6 +67,9 @@
 return Abstract;
   }
 
+  bool isInConstantContext() const { return InConstantContext; }
+  void setInConstantContext(bool 

[PATCH] D131555: [Clang] Propagate const context info when emitting compound literal

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This patch fixes a crash when trying to emit a constant compound literal.

For C++ Clang evaluates either casts or binary operations at translation time,
but doesn't pass on the InConstantContext information that was inferred when
parsing the statement.  Because of this, strict FP evaluation (-ftrapping-math)
which should be in effect yet, then causes checkFloatingpointResult to return
false, which in tryEmitGlobalCompoundLiteral will trigger an assert that the
compound literal wasn't constant.

The discussion here around 'manifestly constant evaluated contexts' was very
helpful to me when trying to understand what LLVM's position is on what
evaluation context should be in effect, together with the explanatory text in
that patch itself:
https://reviews.llvm.org/D87528


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D131555

Files:
  clang/lib/CodeGen/CGExprConstant.cpp
  clang/lib/CodeGen/ConstantEmitter.h
  clang/test/CodeGen/const-init.c


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s 
| FileCheck %s
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu 
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion 
-ffp-exception-behavior=strict -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
@@ -181,3 +181,7 @@
 #pragma pack()
   // CHECK: @g31.a = internal global %struct.anon.2 { i16 23122, i32 
-12312731, i16 -312 }, align 4
 }
+
+struct { const float *floats; } compoundliteral = {
+  (float[1]) { 0.1, },
+};
Index: clang/lib/CodeGen/ConstantEmitter.h
===
--- clang/lib/CodeGen/ConstantEmitter.h
+++ clang/lib/CodeGen/ConstantEmitter.h
@@ -67,6 +67,9 @@
 return Abstract;
   }
 
+  bool isInConstantContext() const { return InConstantContext; }
+  void setInConstantContext(bool var) { InConstantContext = var; }
+
   /// Try to emit the initiaizer of the given declaration as an abstract
   /// constant.  If this succeeds, the emission must be finalized.
   llvm::Constant *tryEmitForInitializer(const VarDecl );
Index: clang/lib/CodeGen/CGExprConstant.cpp
===
--- clang/lib/CodeGen/CGExprConstant.cpp
+++ clang/lib/CodeGen/CGExprConstant.cpp
@@ -913,17 +913,15 @@
 // ConstExprEmitter
 
//===--===//
 
-static ConstantAddress tryEmitGlobalCompoundLiteral(CodeGenModule ,
-CodeGenFunction *CGF,
+static ConstantAddress tryEmitGlobalCompoundLiteral(ConstantEmitter ,
   const CompoundLiteralExpr *E) {
+  CodeGenModule  = emitter.CGM;
   CharUnits Align = CGM.getContext().getTypeAlignInChars(E->getType());
   if (llvm::GlobalVariable *Addr =
   CGM.getAddrOfConstantCompoundLiteralIfEmitted(E))
 return ConstantAddress(Addr, Addr->getValueType(), Align);
 
   LangAS addressSpace = E->getType().getAddressSpace();
-
-  ConstantEmitter emitter(CGM, CGF);
   llvm::Constant *C = emitter.tryEmitForInitializer(E->getInitializer(),
 addressSpace, 
E->getType());
   if (!C) {
@@ -1970,7 +1968,9 @@
 
 ConstantLValue
 ConstantLValueEmitter::VisitCompoundLiteralExpr(const CompoundLiteralExpr *E) {
-  return tryEmitGlobalCompoundLiteral(CGM, Emitter.CGF, E);
+  ConstantEmitter CompoundLiteralEmitter(CGM, Emitter.CGF);
+  CompoundLiteralEmitter.setInConstantContext(Emitter.isInConstantContext());
+  return tryEmitGlobalCompoundLiteral(CompoundLiteralEmitter, E);
 }
 
 ConstantLValue
@@ -2214,7 +2214,8 @@
 ConstantAddress
 CodeGenModule::GetAddrOfConstantCompoundLiteral(const CompoundLiteralExpr *E) {
   assert(E->isFileScope() && "not a file-scope compound literal expr");
-  return tryEmitGlobalCompoundLiteral(*this, nullptr, E);
+  ConstantEmitter emitter(*this, nullptr);
+  return tryEmitGlobalCompoundLiteral(emitter, E);
 }
 
 llvm::Constant *


Index: clang/test/CodeGen/const-init.c
===
--- clang/test/CodeGen/const-init.c
+++ clang/test/CodeGen/const-init.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu -ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -ffp-exception-behavior=strict -emit-llvm -o - 

[PATCH] D123763: [randstruct] Enforce using a designated init for a randomized struct

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Comment at: clang/lib/Sema/SemaInit.cpp:2171
 
 if (Field == FieldEnd) {
   // We've run out of fields. We're done.

@void Unfortunately this end of fields check will break the non-designated 
initializer check below.

I GDB'ed through a failure of the below test, and if I'm understanding this 
correctly, the `CheckDesignatedInitializer` invocation above will move `Field` 
to the next available field in the struct. If there is none, we will break out 
of the loop and never reach the code below (On an AArch64 Linux host the field 
was placed last in the struct).

Instead I get a different error:

error: 'error' diagnostics expected but not seen:
  File /Users/zeno/code/llvm/clean/clang/test/Sema/init-randomized-struct.c 
Line 46: a randomized struct can only be initialized with a designated 
initializer
error: 'error' diagnostics seen but not expected:
  File /Users/zeno/code/llvm/clean/clang/test/Sema/init-randomized-struct.c 
Line 46: excess elements in struct initializer
2 errors generated.

You can replicate this on other build setups by varying the value of 
-frandomoze-layout-seed. On x86_64 Linux and on Aarch64 OSX this worked for me 
(in seed value of lit test, change `f` to `d`):
-frandomize-layout-seed=1234567890abcded

Also, I know this was talked about before, and I know a fix is planned, but 
just to add my two cents: yes, it would be great if the `std::shuffle` could be 
changed to `llvm::shuffle`, also because we're expecting to produced the same 
code across different platforms for safety (compliance) reasons.


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[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

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This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG352453569b2b: [AARCH64] ssbs should be enabled by default 
for cortex-x1, cortex-x1c, cortex… (authored by stuij).

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/test/Driver/aarch64-ssbs.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Target/AArch64/AArch64.td


Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -957,7 +957,7 @@
  FeatureRCPC, FeatureSSBS, FeaturePerfMon];
   list A77  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureFullFP16, FeatureDotProd,
- FeatureRCPC, FeaturePerfMon];
+ FeatureRCPC, FeaturePerfMon, FeatureSSBS];
   list A78  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureFullFP16, FeatureDotProd,
  FeatureRCPC, FeaturePerfMon, FeatureSPE,
@@ -975,11 +975,12 @@
  FeatureSB];
   list X1   = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
- FeatureSPE, FeatureFullFP16, FeatureDotProd];
+ FeatureSPE, FeatureFullFP16, FeatureDotProd,
+ FeatureSSBS];
   list X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
  FeatureSPE, FeatureFullFP16, FeatureDotProd,
- FeaturePAuth];
+ FeaturePAuth, FeatureSSBS];
   list X2   = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
  FeatureMatMulInt8, FeatureBF16, FeatureAM,
  FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -120,6 +120,8 @@
 Features.push_back("+mops");
   if (Extensions & AArch64::AEK_PERFMON)
 Features.push_back("+perfmon");
+  if (Extensions & AArch64::AEK_SSBS)
+Features.push_back("+ssbs");
 
   return true;
 }
Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -285,7 +285,7 @@
 // CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
-// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16"
+// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+ssbs" "-target-feature" 
"+fullfp16"
 // CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" 
"+dotprod" "-target-feature" "+fullfp16"
 // CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
Index: clang/test/Driver/aarch64-ssbs.c

[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

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stuij added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64.td:978
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
  FeatureSPE, FeatureFullFP16, FeatureDotProd];
   list X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,

amilendra wrote:
> stuij wrote:
> > dmgreen wrote:
> > > X1 and A77 missing SSBS too. Should they be added at the same time?
> > Yes they should. Thanks!
> Maybe add unit tests for X1 and A77 too?
I did. See the top file.

In general it'd be good to have better testing for individual cores. This will 
happen more structurally in future changes.


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[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

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stuij added inline comments.



Comment at: clang/test/Preprocessor/aarch64-target-features.c:288
 // CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
-// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16"
+// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+ssbs" "-target-feature" 
"+fullfp16"
 // CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"

DavidSpickett wrote:
> Why did this change, was it just not correct before or is r82 some equivalent 
> of the x1c?
yes, not correct. ssbs was enabled by default for cortex-r82, but we're now 
making sure we're passing +ssbs to the backend, like we do with other 
extensions.



Comment at: llvm/lib/Target/AArch64/AArch64.td:978
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
  FeatureSPE, FeatureFullFP16, FeatureDotProd];
   list X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,

dmgreen wrote:
> X1 and A77 missing SSBS too. Should they be added at the same time?
Yes they should. Thanks!


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[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1c

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stuij updated this revision to Diff 414635.
stuij added a comment.

addressed review comments


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Files:
  clang/test/Driver/aarch64-ssbs.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Target/AArch64/AArch64.td


Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -957,7 +957,7 @@
  FeatureRCPC, FeatureSSBS, FeaturePerfMon];
   list A77  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureFullFP16, FeatureDotProd,
- FeatureRCPC, FeaturePerfMon];
+ FeatureRCPC, FeaturePerfMon, FeatureSSBS];
   list A78  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureFullFP16, FeatureDotProd,
  FeatureRCPC, FeaturePerfMon, FeatureSPE,
@@ -975,11 +975,12 @@
  FeatureSB];
   list X1   = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
- FeatureSPE, FeatureFullFP16, FeatureDotProd];
+ FeatureSPE, FeatureFullFP16, FeatureDotProd,
+ FeatureSSBS];
   list X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
  FeatureSPE, FeatureFullFP16, FeatureDotProd,
- FeaturePAuth];
+ FeaturePAuth, FeatureSSBS];
   list X2   = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
  FeatureMatMulInt8, FeatureBF16, FeatureAM,
  FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -120,6 +120,8 @@
 Features.push_back("+mops");
   if (Extensions & AArch64::AEK_PERFMON)
 Features.push_back("+perfmon");
+  if (Extensions & AArch64::AEK_SSBS)
+Features.push_back("+ssbs");
 
   return true;
 }
Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -285,7 +285,7 @@
 // CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
-// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16"
+// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+ssbs" "-target-feature" 
"+fullfp16"
 // CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" 
"+dotprod" "-target-feature" "+fullfp16"
 // CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
Index: clang/test/Driver/aarch64-ssbs.c
===
--- clang/test/Driver/aarch64-ssbs.c
+++ clang/test/Driver/aarch64-ssbs.c
@@ -1,7 +1,11 @@
 // RUN: %clang -### -target 

[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1c

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stuij created this revision.
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Files:
  clang/test/Driver/aarch64-ssbs.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Target/AArch64/AArch64.td


Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -979,7 +979,7 @@
   list X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
  FeatureSPE, FeatureFullFP16, FeatureDotProd,
- FeaturePAuth];
+ FeaturePAuth, FeatureSSBS];
   list X2   = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
  FeatureMatMulInt8, FeatureBF16, FeatureAM,
  FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -120,6 +120,8 @@
 Features.push_back("+mops");
   if (Extensions & AArch64::AEK_PERFMON)
 Features.push_back("+perfmon");
+  if (Extensions & AArch64::AEK_SSBS)
+Features.push_back("+ssbs");
 
   return true;
 }
Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -285,7 +285,7 @@
 // CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
-// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16"
+// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"  
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" 
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" 
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+ssbs" "-target-feature" 
"+fullfp16"
 // CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" 
"+dotprod" "-target-feature" "+fullfp16"
 // CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" 
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" 
"-target-feature" "+crc" "-target-feature" "+crypto"
Index: clang/test/Driver/aarch64-ssbs.c
===
--- clang/test/Driver/aarch64-ssbs.c
+++ clang/test/Driver/aarch64-ssbs.c
@@ -1,7 +1,9 @@
 // RUN: %clang -### -target aarch64-none-none-eabi -march=armv8a+ssbs   %s 
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1c %s 
2>&1 | FileCheck %s
 // CHECK: "-target-feature" "+ssbs"
 
 // RUN: %clang -### -target aarch64-none-none-eabi -march=armv8a+nossbs %s 
2>&1 | FileCheck %s --check-prefix=NOSSBS
+// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1c+nossbs %s 
2>&1 | FileCheck %s --check-prefix=NOSSBS
 // NOSSBS: "-target-feature" "-ssbs"
 
 // RUN: %clang -### -target aarch64-none-none-eabi  %s 
2>&1 | FileCheck %s --check-prefix=ABSENTSSBS


Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -979,7 +979,7 @@
   list X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,

[PATCH] D119008: Add Cortex-X1C to Clang LLVM 14 release notes

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stuij created this revision.
stuij requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
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https://reviews.llvm.org/D119008

Files:
  clang/docs/ReleaseNotes.rst


Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -101,6 +101,10 @@
   - RISC-V SiFive S51 (``sifive-s51``).
   - RISC-V SiFive S54 (``sifive-s54``).
   - RISC-V SiFive S76 (``sifive-s76``).
+  - Arm Cortex-X1C (``cortex-x1c``)
+  - Arm Cortex-X2 (``cortex-x2``)
+  - Arm Cortex-A510 (``cortex-a510``)
+  - Arm Cortex-A710 (``cortex-a710``)
 
 - Support has been added for the following architectures (``-march`` 
identifiers in parentheses):
 
@@ -281,11 +285,6 @@
 Arm and AArch64 Support in Clang
 
 
-- Support has been added for the following processors (command-line 
identifiers in parentheses):
-  - Arm Cortex-A510 (``cortex-a510``)
-  - Arm Cortex-X2 (``cortex-x2``)
-  - Arm Cortex-A710 (``cortex-A710``)
-
 - The -mtune flag is no longer ignored for AArch64. It is now possible to
   tune code generation for a particular CPU with -mtune without setting any
   architectural features. For example, compiling with


Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -101,6 +101,10 @@
   - RISC-V SiFive S51 (``sifive-s51``).
   - RISC-V SiFive S54 (``sifive-s54``).
   - RISC-V SiFive S76 (``sifive-s76``).
+  - Arm Cortex-X1C (``cortex-x1c``)
+  - Arm Cortex-X2 (``cortex-x2``)
+  - Arm Cortex-A510 (``cortex-a510``)
+  - Arm Cortex-A710 (``cortex-a710``)
 
 - Support has been added for the following architectures (``-march`` identifiers in parentheses):
 
@@ -281,11 +285,6 @@
 Arm and AArch64 Support in Clang
 
 
-- Support has been added for the following processors (command-line identifiers in parentheses):
-  - Arm Cortex-A510 (``cortex-a510``)
-  - Arm Cortex-X2 (``cortex-x2``)
-  - Arm Cortex-A710 (``cortex-A710``)
-
 - The -mtune flag is no longer ignored for AArch64. It is now possible to
   tune code generation for a particular CPU with -mtune without setting any
   architectural features. For example, compiling with
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[PATCH] D118380: Add info on PACBTI-M to the Clang release notes

[Ties Stuij via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1adfbfcf39f9: Add info on PACBTI-M to the Clang release 
notes (authored by stuij).

Repository:
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Files:
  clang/docs/ReleaseNotes.rst


Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -77,6 +77,9 @@
 
 - Clang plugin arguments can now be passed through the compiler driver via
   ``-fplugin-arg-pluginname-arg``, similar to GCC's ``-fplugin-arg``.
+- The ``-mno-bti-at-return-twice`` flag will make sure a BTI instruction won't
+  be added after a setjmp or possible other return-twice construct (ARM backend
+  only).
 
 Deprecated Compiler Flags
 -
@@ -293,6 +296,11 @@
   GNU driver. Programs that depend on clang invoking GCC as the linker driver
   should use GCC as the linker in the build system.
 
+- The ``-mbranch-protection`` flag will now also work for the ARM backend.
+
+- The ``attribute((target("branch-protection=...)))`` attributes will now also
+  work for the ARM backend.
+
 Floating Point Support in Clang
 ---
 - The default setting of FP contraction (FMA) is now -ffp-contract=on (for


Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -77,6 +77,9 @@
 
 - Clang plugin arguments can now be passed through the compiler driver via
   ``-fplugin-arg-pluginname-arg``, similar to GCC's ``-fplugin-arg``.
+- The ``-mno-bti-at-return-twice`` flag will make sure a BTI instruction won't
+  be added after a setjmp or possible other return-twice construct (ARM backend
+  only).
 
 Deprecated Compiler Flags
 -
@@ -293,6 +296,11 @@
   GNU driver. Programs that depend on clang invoking GCC as the linker driver
   should use GCC as the linker in the build system.
 
+- The ``-mbranch-protection`` flag will now also work for the ARM backend.
+
+- The ``attribute((target("branch-protection=...)))`` attributes will now also
+  work for the ARM backend.
+
 Floating Point Support in Clang
 ---
 - The default setting of FP contraction (FMA) is now -ffp-contract=on (for
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[PATCH] D117202: [ARM] Add Cortex-X1C Support for Clang and LLVM

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This revision was automatically updated to reflect the committed changes.
Closed by commit rG6b1e844b69f1: [ARM] Add Cortex-X1C Support for Clang and 
LLVM (authored by stuij).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -333,7 +333,13 @@
  ARM::AEK_RAS | ARM::AEK_FP16 | ARM::AEK_DOTPROD |
  ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
  ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
- ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS,
+ ARM::AEK_DSP | ARM::AEK_CRC,
+ "8.2-A"),
+ARMCPUTestParams("cortex-x1c", "armv8.2-a", "crypto-neon-fp-armv8",
+ ARM::AEK_RAS | ARM::AEK_FP16 | ARM::AEK_DOTPROD |
+ ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
+ ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
+ ARM::AEK_DSP | ARM::AEK_CRC,
  "8.2-A"),
 ARMCPUTestParams("neoverse-n1", "armv8.2-a", "crypto-neon-fp-armv8",
  ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
@@ -394,7 +400,7 @@
  ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
  "7-S")));
 
-static constexpr unsigned NumARMCPUArchs = 87;
+static constexpr unsigned NumARMCPUArchs = 88;
 
 TEST(TargetParserTest, testARMCPUArchList) {
   SmallVector List;
@@ -1035,6 +1041,14 @@
  AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
  AArch64::AEK_SSBS,
  "8.2-A"),
+ARMCPUTestParams("cortex-x1c", "armv8.2-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+ AArch64::AEK_FP | AArch64::AEK_RDM |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS |
+ AArch64::AEK_LSE | AArch64::AEK_FP16 |
+ AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
+ AArch64::AEK_SSBS | AArch64::AEK_PAUTH,
+ "8.2-A"),
 ARMCPUTestParams("cortex-x2", "armv9-a", "neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_FP |
  AArch64::AEK_SIMD | AArch64::AEK_RAS |
@@ -1235,7 +1249,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 52;
+static constexpr unsigned NumAArch64CPUArchs = 53;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/lib/Target/ARM/ARMSubtarget.h
===
--- llvm/lib/Target/ARM/ARMSubtarget.h
+++ llvm/lib/Target/ARM/ARMSubtarget.h
@@ -77,6 +77,7 @@
 CortexR52,
 CortexR7,
 CortexX1,
+CortexX1C,
 Exynos,
 Krait,
 Kryo,
Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -304,6 +304,7 @@
   case CortexM7:
   case CortexR52:
   case CortexX1:
+  case CortexX1C:
 break;
   case Exynos:
 LdStMultipleTiming = SingleIssuePlusExtras;
Index: llvm/lib/Target/ARM/ARM.td
===
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -656,6 +656,8 @@
"CortexA710", "Cortex-A710 ARM processors", []>;
 def ProcX1  : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
"Cortex-X1 ARM processors", []>;
+def ProcX1C : SubtargetFeature<"cortex-x1c", "ARMProcFamily", "CortexX1C",
+   "Cortex-X1C ARM processors", []>;
 
 def ProcV1  : SubtargetFeature<"neoverse-v1", "ARMProcFamily",
"NeoverseV1", "Neoverse-V1 ARM processors", []>;
@@ -1443,6 +1445,14 @@
 

[PATCH] D118380: Add info on PACBTI-M to the Clang release notes

[Ties Stuij via Phabricator via cfe-commits]

stuij created this revision.
stuij requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
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https://reviews.llvm.org/D118380

Files:
  clang/docs/ReleaseNotes.rst


Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -77,6 +77,9 @@
 
 - Clang plugin arguments can now be passed through the compiler driver via
   ``-fplugin-arg-pluginname-arg``, similar to GCC's ``-fplugin-arg``.
+- The ``-mno-bti-at-return-twice`` flag will make sure a BTI instruction won't
+  be added after a setjmp or possible other return-twice construct (ARM backend
+  only).
 
 Deprecated Compiler Flags
 -
@@ -279,6 +282,11 @@
   GNU driver. Programs that depend on clang invoking GCC as the linker driver
   should use GCC as the linker in the build system.
 
+- The ``-mbranch-protection`` flag will now also work for the ARM backend.
+
+- The ``attribute((target("branch-protection=...)))`` attributes will now also
+  work for the ARM backend.
+
 Floating Point Support in Clang
 ---
 - The default setting of FP contraction (FMA) is now -ffp-contract=on (for


Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -77,6 +77,9 @@
 
 - Clang plugin arguments can now be passed through the compiler driver via
   ``-fplugin-arg-pluginname-arg``, similar to GCC's ``-fplugin-arg``.
+- The ``-mno-bti-at-return-twice`` flag will make sure a BTI instruction won't
+  be added after a setjmp or possible other return-twice construct (ARM backend
+  only).
 
 Deprecated Compiler Flags
 -
@@ -279,6 +282,11 @@
   GNU driver. Programs that depend on clang invoking GCC as the linker driver
   should use GCC as the linker in the build system.
 
+- The ``-mbranch-protection`` flag will now also work for the ARM backend.
+
+- The ``attribute((target("branch-protection=...)))`` attributes will now also
+  work for the ARM backend.
+
 Floating Point Support in Clang
 ---
 - The default setting of FP contraction (FMA) is now -ffp-contract=on (for
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[PATCH] D117202: [ARM] Add Cortex-X1C Support for Clang and LLVM

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Herald added a subscriber: dexonsmith.

addressed review comments


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Files:
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -332,7 +332,13 @@
  ARM::AEK_RAS | ARM::AEK_FP16 | ARM::AEK_DOTPROD |
  ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
  ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
- ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS,
+ ARM::AEK_DSP | ARM::AEK_CRC,
+ "8.2-A"),
+ARMCPUTestParams("cortex-x1c", "armv8.2-a", "crypto-neon-fp-armv8",
+ ARM::AEK_RAS | ARM::AEK_FP16 | ARM::AEK_DOTPROD |
+ ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
+ ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
+ ARM::AEK_DSP | ARM::AEK_CRC,
  "8.2-A"),
 ARMCPUTestParams("neoverse-n1", "armv8.2-a", "crypto-neon-fp-armv8",
  ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
@@ -393,7 +399,7 @@
  ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
  "7-S")));
 
-static constexpr unsigned NumARMCPUArchs = 87;
+static constexpr unsigned NumARMCPUArchs = 88;
 
 TEST(TargetParserTest, testARMCPUArchList) {
   SmallVector List;
@@ -1032,6 +1038,14 @@
  AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
  AArch64::AEK_SSBS,
  "8.2-A"),
+ARMCPUTestParams("cortex-x1c", "armv8.2-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+ AArch64::AEK_FP | AArch64::AEK_RDM |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS |
+ AArch64::AEK_LSE | AArch64::AEK_FP16 |
+ AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
+ AArch64::AEK_SSBS | AArch64::AEK_PAUTH,
+ "8.2-A"),
 ARMCPUTestParams("cortex-x2", "armv9-a", "neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_FP |
  AArch64::AEK_SIMD | AArch64::AEK_RAS |
@@ -1232,7 +1246,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 52;
+static constexpr unsigned NumAArch64CPUArchs = 53;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/lib/Target/ARM/ARMSubtarget.h
===
--- llvm/lib/Target/ARM/ARMSubtarget.h
+++ llvm/lib/Target/ARM/ARMSubtarget.h
@@ -77,6 +77,7 @@
 CortexR52,
 CortexR7,
 CortexX1,
+CortexX1C,
 Exynos,
 Krait,
 Kryo,
Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -304,6 +304,7 @@
   case CortexM7:
   case CortexR52:
   case CortexX1:
+  case CortexX1C:
 break;
   case Exynos:
 LdStMultipleTiming = SingleIssuePlusExtras;
Index: llvm/lib/Target/ARM/ARM.td
===
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -656,6 +656,8 @@
"CortexA710", "Cortex-A710 ARM processors", []>;
 def ProcX1  : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
"Cortex-X1 ARM processors", []>;
+def ProcX1C : SubtargetFeature<"cortex-x1c", "ARMProcFamily", "CortexX1C",
+   "Cortex-X1C ARM processors", []>;
 
 def ProcV1  : SubtargetFeature<"neoverse-v1", "ARMProcFamily",
"NeoverseV1", "Neoverse-V1 ARM processors", []>;
@@ -1443,6 +1445,14 @@

[PATCH] D117202: [ARM] Add Cortex-X1C Support for Clang and LLVM

[Ties Stuij via Phabricator via cfe-commits]

stuij marked 2 inline comments as done.
stuij added a comment.

> Thanks for the update. Same(ish) questions for the Arm side. Otherwise this 
> LGTM

Ai, thanks. Should have checked Arm as well.

> Oh, also is there an ID for this CPU that is worth adding to 
> getHostCPUNameForARM in Host.cpp?

Yup, thanks. Added.




Comment at: llvm/lib/Target/ARM/ARM.td:1446
 
+def : ProcNoItin<"cortex-x1c",  [ARMv82a,
+ FeatureHWDivThumb,

dmgreen wrote:
> Should this have ProcX1C added?
yes :)


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Files:
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -334,6 +334,12 @@
  ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
  ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS,
  "8.2-A"),
+ARMCPUTestParams("cortex-x1c", "armv8.2-a", "crypto-neon-fp-armv8",
+ ARM::AEK_RAS | ARM::AEK_SEC | ARM::AEK_MP |
+ ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+ ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC |
+ ARM::AEK_RAS,
+ "8.2-A"),
 ARMCPUTestParams("neoverse-n1", "armv8.2-a", "crypto-neon-fp-armv8",
  ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
  ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
@@ -393,7 +399,7 @@
  ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
  "7-S")));
 
-static constexpr unsigned NumARMCPUArchs = 87;
+static constexpr unsigned NumARMCPUArchs = 88;
 
 TEST(TargetParserTest, testARMCPUArchList) {
   SmallVector List;
@@ -1032,6 +1038,14 @@
  AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
  AArch64::AEK_SSBS,
  "8.2-A"),
+ARMCPUTestParams("cortex-x1c", "armv8.2-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+ AArch64::AEK_FP | AArch64::AEK_RDM |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS |
+ AArch64::AEK_LSE | AArch64::AEK_FP16 |
+ AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
+ AArch64::AEK_SSBS | AArch64::AEK_PAUTH,
+ "8.2-A"),
 ARMCPUTestParams("cortex-x2", "armv9-a", "neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_FP |
  AArch64::AEK_SIMD | AArch64::AEK_RAS |
@@ -1232,7 +1246,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 52;
+static constexpr unsigned NumAArch64CPUArchs = 53;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/lib/Target/ARM/ARMSubtarget.h
===
--- llvm/lib/Target/ARM/ARMSubtarget.h
+++ llvm/lib/Target/ARM/ARMSubtarget.h
@@ -77,6 +77,7 @@
 CortexR52,
 CortexR7,
 CortexX1,
+CortexX1C,
 Exynos,
 Krait,
 Kryo,
Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -304,6 +304,7 @@
   case CortexM7:
   case CortexR52:
   case CortexX1:
+  case CortexX1C:
 break;
   case Exynos:
 LdStMultipleTiming = SingleIssuePlusExtras;
Index: llvm/lib/Target/ARM/ARM.td
===
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -657,6 +657,8 @@
"CortexA710", "Cortex-A710 ARM processors", []>;
 def ProcX1  : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
"Cortex-X1 ARM processors", []>;
+def ProcX1C : SubtargetFeature<"cortex-x1c", "ARMProcFamily", "CortexX1C",
+   "Cortex-X1C ARM processors", []>;
 
 def ProcV1  : SubtargetFeature<"neoverse-v1", "ARMProcFamily",
"NeoverseV1", "Neoverse-V1 ARM processors", []>;
@@ -1441,6 +1443,13 @@
  FeatureFullFP16,
  FeatureDotProd]>;
 
+def : ProcNoItin<"cortex-x1c",  [ARMv82a,
+ 

[PATCH] D117202: [ARM] Add Cortex-X1C Support for Clang and LLVM

[Ties Stuij via Phabricator via cfe-commits]

stuij marked 2 inline comments as done.
stuij added inline comments.



Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:205
+AARCH64_CPU_NAME("cortex-x1c", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (AArch64::AEK_RAS))
 AARCH64_CPU_NAME("cortex-x2", ARMV9A, FK_NEON_FP_ARMV8, false,

dmgreen wrote:
> Should this have the same features as the cortex-x1? AEK_DOTPROD and AEK_FP16 
> and the rest?
Yes, you're right. I've added these.



Comment at: llvm/lib/Target/AArch64/AArch64.td:983
+ FeatureNEON, FeaturePerfMon, FeatureSPE,
+ FeaturePAuth, FeatureFullFP16, 
FeatureFP16FML];
   list X2   = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,

dmgreen wrote:
> Should this have dotprod and RCPC?
> 
> The TRM isn't super clear on what features are present. Is FP16FML present?
Right, the addition of FP16FML must have been copied from the X1, which was 
later removed when upstreaming. I removed it here, and I added dotard and RCPC. 
The only relevant change from X1 to X1C is the addition of PAUTH, as per the 
TRM.


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[PATCH] D117202: [ARM] Add Cortex-X1C Support for Clang and LLVM

[Ties Stuij via Phabricator via cfe-commits]

stuij created this revision.
Herald added subscribers: hiraditya, kristof.beyls.
stuij requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch upstreams support for the Arm-v8 Cortex-X1C processor for AArch64 and
ARM.

For more information, see:

- 
https://community.arm.com/arm-community-blogs/b/announcements/posts/arm-cortex-x1c
- 
https://developer.arm.com/documentation/101968/0002/Functional-description/Technical-overview/Components

The following people contributed to this patch:

- Simon Tatham
- Ties Stuij


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117202

Files:
  clang/test/Driver/aarch64-cpus.c
  clang/test/Driver/arm-cortex-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -334,6 +334,12 @@
  ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
  ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS,
  "8.2-A"),
+ARMCPUTestParams("cortex-x1c", "armv8.2-a", "crypto-neon-fp-armv8",
+ ARM::AEK_RAS | ARM::AEK_SEC | ARM::AEK_MP |
+ ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+ ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC |
+ ARM::AEK_RAS,
+ "8.2-A"),
 ARMCPUTestParams("neoverse-n1", "armv8.2-a", "crypto-neon-fp-armv8",
  ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
  ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
@@ -393,7 +399,7 @@
  ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
  "7-S")));
 
-static constexpr unsigned NumARMCPUArchs = 87;
+static constexpr unsigned NumARMCPUArchs = 88;
 
 TEST(TargetParserTest, testARMCPUArchList) {
   SmallVector List;
@@ -1032,6 +1038,12 @@
  AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
  AArch64::AEK_SSBS,
  "8.2-A"),
+ARMCPUTestParams("cortex-x1c", "armv8.2-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+ AArch64::AEK_FP | AArch64::AEK_RDM |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS |
+ AArch64::AEK_LSE,
+ "8.2-A"),
 ARMCPUTestParams("cortex-x2", "armv9-a", "neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_FP |
  AArch64::AEK_SIMD | AArch64::AEK_RAS |
@@ -1232,7 +1244,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 52;
+static constexpr unsigned NumAArch64CPUArchs = 53;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/lib/Target/ARM/ARMSubtarget.h
===
--- llvm/lib/Target/ARM/ARMSubtarget.h
+++ llvm/lib/Target/ARM/ARMSubtarget.h
@@ -77,6 +77,7 @@
 CortexR52,
 CortexR7,
 CortexX1,
+CortexX1C,
 Exynos,
 Krait,
 Kryo,
Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -304,6 +304,7 @@
   case CortexM7:
   case CortexR52:
   case CortexX1:
+  case CortexX1C:
 break;
   case Exynos:
 LdStMultipleTiming = SingleIssuePlusExtras;
Index: llvm/lib/Target/ARM/ARM.td
===
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -657,6 +657,8 @@
"CortexA710", "Cortex-A710 ARM processors", []>;
 def ProcX1  : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
"Cortex-X1 ARM processors", []>;
+def ProcX1C : SubtargetFeature<"cortex-x1c", "ARMProcFamily", "CortexX1C",
+   "Cortex-X1C ARM processors", []>;
 
 def ProcV1  : SubtargetFeature<"neoverse-v1", "ARMProcFamily",
"NeoverseV1", "Neoverse-V1 ARM processors", []>;
@@ -1441,6 +1443,13 @@
 

[PATCH] D116509: [Builtins] Add missing the macro 'y' description in comments

[Ties Stuij via Phabricator via cfe-commits]

stuij accepted this revision.
stuij added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!

Nit: perhaps make the commit message a little bit clearer.


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[PATCH] D115507: Add PACBTI-M support to LLVM release notes.

[Ties Stuij via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGfbf489cd1b4b: Add PACBTI-M support to LLVM release notes. 
(authored by stuij).

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  llvm/docs/ReleaseNotes.rst


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -83,6 +83,7 @@
 --
 
 * Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
+* Added support for the Armv8.1-M PACBTI-M extension.
 
 Changes to the MIPS Target
 --


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -83,6 +83,7 @@
 --
 
 * Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
+* Added support for the Armv8.1-M PACBTI-M extension.
 
 Changes to the MIPS Target
 --
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[PATCH] D115507: Add PACBTI-M support to LLVM release notes.

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 393434.
stuij added a comment.

removed accidentally included Clang release notes draft


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Files:
  llvm/docs/ReleaseNotes.rst


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -83,6 +83,7 @@
 --
 
 * Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
+* Added support for the Armv8.1-M PACBTI-M extension.
 
 Changes to the MIPS Target
 --


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -83,6 +83,7 @@
 --
 
 * Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
+* Added support for the Armv8.1-M PACBTI-M extension.
 
 Changes to the MIPS Target
 --
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[PATCH] D115507: Add PACBTI-M support to LLVM release notes.

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stuij created this revision.
stuij requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Clang release note changes will be added once the last PACBTI-M command line
patch lands.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115507

Files:
  clang/docs/ReleaseNotes.rst
  llvm/docs/ReleaseNotes.rst


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -83,6 +83,7 @@
 --
 
 * Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
+* Added support for the Armv8.1-M PACBTI-M extension.
 
 Changes to the MIPS Target
 --
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -69,6 +69,9 @@
 
 - Clang plugin arguments can now be passed through the compiler driver via
   ``-fplugin-arg-pluginname-arg``, similar to GCC's ``-fplugin-arg``.
+- The ``-mbranch-protection`` flag will now also work for the ARM backend
+- The ``-mno-bti-at-return-twice`` flag will make sure a BTI instruction won't
+  be added after a setjmp or other return-twice construct (ARM backend only).
 
 Deprecated Compiler Flags
 -
@@ -226,6 +229,8 @@
   architecture features, but will enable certain optimizations specific to
   Cortex-A57 CPUs and enable the use of a more accurate scheduling model.
 
+Do not add a BTI instruction after a setjmp or other return-twice construct 
(Arm
+only)
 
 Floating Point Support in Clang
 ---


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -83,6 +83,7 @@
 --
 
 * Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
+* Added support for the Armv8.1-M PACBTI-M extension.
 
 Changes to the MIPS Target
 --
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -69,6 +69,9 @@
 
 - Clang plugin arguments can now be passed through the compiler driver via
   ``-fplugin-arg-pluginname-arg``, similar to GCC's ``-fplugin-arg``.
+- The ``-mbranch-protection`` flag will now also work for the ARM backend
+- The ``-mno-bti-at-return-twice`` flag will make sure a BTI instruction won't
+  be added after a setjmp or other return-twice construct (ARM backend only).
 
 Deprecated Compiler Flags
 -
@@ -226,6 +229,8 @@
   architecture features, but will enable certain optimizations specific to
   Cortex-A57 CPUs and enable the use of a more accurate scheduling model.
 
+Do not add a BTI instruction after a setjmp or other return-twice construct (Arm
+only)
 
 Floating Point Support in Clang
 ---
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[PATCH] D115140: [ARM][clang] Option b-key must not affect __ARM_FEATURE_PAC_DEFAULT

[Ties Stuij via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGbfe07195bb1f: [ARM][clang] Option b-key must not affect 
__ARM_FEATURE_PAC_DEFAULT (authored by stuij).

Repository:
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Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/test/Preprocessor/arm-target-features.c


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -881,20 +881,18 @@
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-BTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-BTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-BTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
 // CHECK-NOBTI-NOT: #define __ARM_FEATURE_BTI_DEFAULT
 // CHECK-NOPAC-NOT: #define __ARM_FEATURE_PAC_DEFAULT
 // CHECK-BTI: #define __ARM_FEATURE_BTI_DEFAULT 1
 // CHECK-PAC: #define __ARM_FEATURE_PAC_DEFAULT 1
-// CHECK-PAC-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 2
 // CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
-// CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
 
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI-EXT,CHECK-NOPAC-EXT %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv7-m+pacbti -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-PACBTI-EXT %s
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -911,7 +911,7 @@
 Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
 
   if (Opts.hasSignReturnAddress()) {
-unsigned Value = Opts.isSignReturnAddressWithAKey() ? 1 : 2;
+unsigned Value = 1;
 if (Opts.isSignReturnAddressScopeAll())
   Value |= 1 << 2;
 Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", Twine(Value));


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -881,20 +881,18 @@
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=bti -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-BTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret -x c -E -dM %s -o - | 

[PATCH] D115140: [ARM][clang] Option b-key must not affect __ARM_FEATURE_PAC_DEFAULT

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 393096.
stuij added a comment.

rebasing


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115140/new/

https://reviews.llvm.org/D115140

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/test/Preprocessor/arm-target-features.c


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -881,20 +881,18 @@
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-BTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-BTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-BTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
 // CHECK-NOBTI-NOT: #define __ARM_FEATURE_BTI_DEFAULT
 // CHECK-NOPAC-NOT: #define __ARM_FEATURE_PAC_DEFAULT
 // CHECK-BTI: #define __ARM_FEATURE_BTI_DEFAULT 1
 // CHECK-PAC: #define __ARM_FEATURE_PAC_DEFAULT 1
-// CHECK-PAC-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 2
 // CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
-// CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
 
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI-EXT,CHECK-NOPAC-EXT %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv7-m+pacbti -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-PACBTI-EXT %s
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -911,7 +911,7 @@
 Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
 
   if (Opts.hasSignReturnAddress()) {
-unsigned Value = Opts.isSignReturnAddressWithAKey() ? 1 : 2;
+unsigned Value = 1;
 if (Opts.isSignReturnAddressScopeAll())
   Value |= 1 << 2;
 Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", Twine(Value));


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -881,20 +881,18 @@
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=bti -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-BTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-PAC,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 

[PATCH] D112431: [ARM][clang] Define feature test macro for the PACBTI-M extension

[Ties Stuij via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGe32b818db187: [ARM][clang] Define feature test macro for the 
PACBTI-M extension (authored by stuij).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112431/new/

https://reviews.llvm.org/D112431

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/test/Preprocessor/arm-target-features.c


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -896,6 +896,13 @@
 // CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
 // CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
 
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI-EXT,CHECK-NOPAC-EXT %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv7-m+pacbti -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-PACBTI-EXT %s
+// CHECK-NOBTI-EXT-NOT: #define __ARM_FEATURE_BTI 1
+// CHECK-NOPAC-EXT-NOT: #define __ARM_FEATURE_PAUTH 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_BTI 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_PAUTH 1
+
 // == Check BFloat16 Extensions.
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.6-a+bf16 -x c -E -dM %s 
-o - 2>&1 | FileCheck -check-prefix=CHECK-BFLOAT %s
 // CHECK-BFLOAT: #define __ARM_BF16_FORMAT_ALTERNATIVE 1
Index: clang/lib/Basic/Targets/ARM.h
===
--- clang/lib/Basic/Targets/ARM.h
+++ clang/lib/Basic/Targets/ARM.h
@@ -79,6 +79,8 @@
   unsigned DotProd : 1;
   unsigned HasMatMul : 1;
   unsigned FPRegsDisabled : 1;
+  unsigned HasPAC : 1;
+  unsigned HasBTI : 1;
 
   enum {
 LDREX_B = (1 << 0), /// byte (8-bit)
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -465,6 +465,8 @@
   HWDiv = 0;
   DotProd = 0;
   HasMatMul = 0;
+  HasPAC = 0;
+  HasBTI = 0;
   HasFloat16 = true;
   ARMCDECoprocMask = 0;
   HasBFloat16 = false;
@@ -547,6 +549,9 @@
   HasBFloat16 = true;
 } else if (Feature == "-fpregs") {
   FPRegsDisabled = true;
+} else if (Feature == "+pacbti") {
+  HasPAC = 1;
+  HasBTI = 1;
 }
   }
 
@@ -890,6 +895,12 @@
   if (HasMatMul)
 Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
 
+  if (HasPAC)
+Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
+
+  if (HasBTI)
+Builder.defineMacro("__ARM_FEATURE_BTI", "1");
+
   if (HasBFloat16) {
 Builder.defineMacro("__ARM_FEATURE_BF16", "1");
 Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -896,6 +896,13 @@
 // CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
 // CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
 
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-NOBTI-EXT,CHECK-NOPAC-EXT %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv7-m+pacbti -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-PACBTI-EXT %s
+// CHECK-NOBTI-EXT-NOT: #define __ARM_FEATURE_BTI 1
+// CHECK-NOPAC-EXT-NOT: #define __ARM_FEATURE_PAUTH 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_BTI 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_PAUTH 1
+
 // == Check BFloat16 Extensions.
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.6-a+bf16 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-BFLOAT %s
 // CHECK-BFLOAT: #define __ARM_BF16_FORMAT_ALTERNATIVE 1
Index: clang/lib/Basic/Targets/ARM.h
===
--- clang/lib/Basic/Targets/ARM.h
+++ clang/lib/Basic/Targets/ARM.h
@@ -79,6 +79,8 @@
   unsigned DotProd : 1;
   unsigned HasMatMul : 1;
   unsigned FPRegsDisabled : 1;
+  unsigned HasPAC : 1;
+  unsigned HasBTI : 1;
 
   enum {
 LDREX_B = (1 << 0), /// byte (8-bit)
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -465,6 +465,8 @@
   HWDiv = 0;
   DotProd = 0;
   HasMatMul = 0;
+  HasPAC = 0;
+  HasBTI = 0;
   HasFloat16 = true;
   ARMCDECoprocMask = 0;
   HasBFloat16 = false;
@@ -547,6 +549,9 @@
   HasBFloat16 = true;
 } else if (Feature == "-fpregs") {
   FPRegsDisabled = true;
+} else if (Feature == "+pacbti") {
+  HasPAC = 1;
+  HasBTI = 1;
 }
   }
 
@@ -890,6 +895,12 @@
   if (HasMatMul)
 Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", 

[PATCH] D112430: [ARM][libunwind] add PACBTI-M support for libunwind

[Ties Stuij via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe6d0b851f854: [ARM][libunwind] add PACBTI-M support for 
libunwind (authored by stuij).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112430/new/

https://reviews.llvm.org/D112430

Files:
  clang/lib/Headers/unwind.h
  libunwind/include/libunwind.h
  libunwind/include/unwind_arm_ehabi.h
  libunwind/src/DwarfInstructions.hpp
  libunwind/src/Registers.hpp
  libunwind/src/Unwind-EHABI.cpp
  libunwind/src/UnwindCursor.hpp
  libunwind/src/UnwindRegistersRestore.S
  libunwind/src/assembly.h

Index: libunwind/src/assembly.h
===
--- libunwind/src/assembly.h
+++ libunwind/src/assembly.h
@@ -81,7 +81,7 @@
 #define PPC64_OPD2
 #endif
 
-#if defined(__ARM_FEATURE_BTI_DEFAULT)
+#if defined(__aarch64__) && defined(__ARM_FEATURE_BTI_DEFAULT)
   .pushsection ".note.gnu.property", "a" SEPARATOR \
   .balign 8 SEPARATOR  \
   .long 4 SEPARATOR\
@@ -99,6 +99,17 @@
 #define AARCH64_BTI
 #endif
 
+#if !defined(__aarch64__)
+#ifdef __ARM_FEATURE_PAC_DEFAULT
+  .eabi_attribute Tag_PAC_extension, 2
+  .eabi_attribute Tag_PACRET_use, 1
+#endif
+#ifdef __ARM_FEATURE_BTI_DEFAULT
+  .eabi_attribute Tag_BTI_extension, 1
+  .eabi_attribute Tag_BTI_use, 1
+#endif
+#endif
+
 #define GLUE2(a, b) a ## b
 #define GLUE(a, b) GLUE2(a, b)
 #define SYMBOL_NAME(name) GLUE(__USER_LABEL_PREFIX__, name)
Index: libunwind/src/UnwindRegistersRestore.S
===
--- libunwind/src/UnwindRegistersRestore.S
+++ libunwind/src/UnwindRegistersRestore.S
@@ -660,7 +660,13 @@
   ldr sp, [lr, #52]
   ldr lr, [lr, #60]  @ restore pc into lr
 #endif
+#if defined(__ARM_FEATURE_BTI_DEFAULT) && !defined(__ARM_ARCH_ISA_ARM)
+  // 'bx' is not BTI setting when used with lr, therefore r12 is used instead
+  mov r12, lr
+  JMP(r12)
+#else
   JMP(lr)
+#endif
 
 @
 @ static void libunwind::Registers_arm::restoreVFPWithFLDMD(unw_fpreg_t* values)
Index: libunwind/src/UnwindCursor.hpp
===
--- libunwind/src/UnwindCursor.hpp
+++ libunwind/src/UnwindCursor.hpp
@@ -655,7 +655,9 @@
 #if defined(_LIBUNWIND_TARGET_X86_64)
   if (regNum >= UNW_X86_64_RAX && regNum <= UNW_X86_64_R15) return true;
 #elif defined(_LIBUNWIND_TARGET_ARM)
-  if (regNum >= UNW_ARM_R0 && regNum <= UNW_ARM_R15) return true;
+  if ((regNum >= UNW_ARM_R0 && regNum <= UNW_ARM_R15) ||
+  regNum == UNW_ARM_RA_AUTH_CODE)
+return true;
 #elif defined(_LIBUNWIND_TARGET_AARCH64)
   if (regNum >= UNW_AARCH64_X0 && regNum <= UNW_ARM64_X30) return true;
 #endif
Index: libunwind/src/Unwind-EHABI.cpp
===
--- libunwind/src/Unwind-EHABI.cpp
+++ libunwind/src/Unwind-EHABI.cpp
@@ -261,6 +261,7 @@
   size_t offset, size_t len) {
   bool wrotePC = false;
   bool finish = false;
+  bool hasReturnAddrAuthCode = false;
   while (offset < len && !finish) {
 uint8_t byte = getByte(data, offset++);
 if ((byte & 0x80) == 0) {
@@ -347,6 +348,10 @@
   break;
 }
 case 0xb4:
+  hasReturnAddrAuthCode = true;
+  _Unwind_VRS_Pop(context, _UVRSC_PSEUDO,
+  0 /* Return Address Auth Code */, _UVRSD_UINT32);
+  break;
 case 0xb5:
 case 0xb6:
 case 0xb7:
@@ -422,6 +427,16 @@
   if (!wrotePC) {
 uint32_t lr;
 _Unwind_VRS_Get(context, _UVRSC_CORE, UNW_ARM_LR, _UVRSD_UINT32, );
+#ifdef __ARM_FEATURE_PAUTH
+if (hasReturnAddrAuthCode) {
+  uint32_t sp;
+  uint32_t pac;
+  _Unwind_VRS_Get(context, _UVRSC_CORE, UNW_ARM_SP, _UVRSD_UINT32, );
+  _Unwind_VRS_Get(context, _UVRSC_PSEUDO, UNW_ARM_RA_AUTH_CODE,
+  _UVRSD_UINT32, );
+  __asm__ __volatile__("autg %0, %1, %2" : : "r"(pac), "r"(lr), "r"(sp) :);
+}
+#endif
 _Unwind_VRS_Set(context, _UVRSC_CORE, UNW_ARM_IP, _UVRSD_UINT32, );
   }
   return _URC_CONTINUE_UNWIND;
@@ -941,6 +956,15 @@
 case _UVRSC_WMMXD:
   break;
 #endif
+case _UVRSC_PSEUDO:
+  // There's only one pseudo-register, PAC, with regno == 0.
+  if (representation != _UVRSD_UINT32 || regno != 0)
+return _UVRSR_FAILED;
+  return __unw_set_reg(cursor, (unw_regnum_t)(UNW_ARM_RA_AUTH_CODE),
+   *(unw_word_t *)valuep) == UNW_ESUCCESS
+ ? _UVRSR_OK
+ : _UVRSR_FAILED;
+  break;
   }
   _LIBUNWIND_ABORT("unsupported register class");
 }
@@ -995,6 +1019,15 @@
 case _UVRSC_WMMXD:
   break;
 #endif
+case _UVRSC_PSEUDO:
+  // There's only 

[PATCH] D115140: [ARM][clang] Option b-key must not affect __ARM_FEATURE_PAC_DEFAULT

[Ties Stuij via Phabricator via cfe-commits]

stuij added a comment.

@danielkiss Yes that needs to be addressed, but we are doing that in another 
patch that will (hopefully) cover all permutations of architecture and branch 
protection values on both the cmdline and as function attributes.

So this patch is just about not having logic in the ARM code that shouldn't be 
there.


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[PATCH] D115141: [ARM][clang] Add back branch protection tests

[Ties Stuij via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG53154a83aee0: [ARM][clang] Add back branch protection tests 
(authored by stuij).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/test/Frontend/arm-invalid-branch-protection.c


Index: clang/test/Frontend/arm-invalid-branch-protection.c
===
--- /dev/null
+++ clang/test/Frontend/arm-invalid-branch-protection.c
@@ -0,0 +1,7 @@
+// REQUIRES: arm-registered-target
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key -c 
%s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi 
-mbranch-protection=pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key 
-c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi 
-mbranch-protection=bti+pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck 
%s
+
+// CHECK: warning: invalid branch protection option 'b-key' in 
'-mbranch-protection={{[a-z+-]*}}' [-Wbranch-protection]


Index: clang/test/Frontend/arm-invalid-branch-protection.c
===
--- /dev/null
+++ clang/test/Frontend/arm-invalid-branch-protection.c
@@ -0,0 +1,7 @@
+// REQUIRES: arm-registered-target
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
+
+// CHECK: warning: invalid branch protection option 'b-key' in '-mbranch-protection={{[a-z+-]*}}' [-Wbranch-protection]
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[PATCH] D115140: [ARM][clang] Option b-key must not affect __ARM_FEATURE_PAC_DEFAULT

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 392021.
stuij added a comment.

another tickle


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115140/new/

https://reviews.llvm.org/D115140

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/test/Preprocessor/arm-target-features.c


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -881,20 +881,18 @@
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-BTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-BTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-BTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
 // CHECK-NOBTI-NOT: #define __ARM_FEATURE_BTI_DEFAULT
 // CHECK-NOPAC-NOT: #define __ARM_FEATURE_PAC_DEFAULT
 // CHECK-BTI: #define __ARM_FEATURE_BTI_DEFAULT 1
 // CHECK-PAC: #define __ARM_FEATURE_PAC_DEFAULT 1
-// CHECK-PAC-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 2
 // CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
-// CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
 
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI-EXT,CHECK-NOPAC-EXT %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv7-m+pacbti -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-PACBTI-EXT %s
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -911,7 +911,7 @@
 Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
 
   if (Opts.hasSignReturnAddress()) {
-unsigned Value = Opts.isSignReturnAddressWithAKey() ? 1 : 2;
+unsigned Value = 1;
 if (Opts.isSignReturnAddressScopeAll())
   Value |= 1 << 2;
 Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", Twine(Value));


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -881,20 +881,18 @@
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=bti -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-BTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-PAC,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 

[PATCH] D115140: [ARM][clang] Option b-key must not affect __ARM_FEATURE_PAC_DEFAULT

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 392013.
stuij added a comment.

tickling the commit so the buildbot picks up the dependency


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115140/new/

https://reviews.llvm.org/D115140

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/test/Preprocessor/arm-target-features.c


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -881,20 +881,18 @@
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-BTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-BTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-BTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
 // CHECK-NOBTI-NOT: #define __ARM_FEATURE_BTI_DEFAULT
 // CHECK-NOPAC-NOT: #define __ARM_FEATURE_PAC_DEFAULT
 // CHECK-BTI: #define __ARM_FEATURE_BTI_DEFAULT 1
 // CHECK-PAC: #define __ARM_FEATURE_PAC_DEFAULT 1
-// CHECK-PAC-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 2
 // CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
-// CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
 
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI-EXT,CHECK-NOPAC-EXT %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv7-m+pacbti -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-PACBTI-EXT %s
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -911,7 +911,7 @@
 Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
 
   if (Opts.hasSignReturnAddress()) {
-unsigned Value = Opts.isSignReturnAddressWithAKey() ? 1 : 2;
+unsigned Value = 1;
 if (Opts.isSignReturnAddressScopeAll())
   Value |= 1 << 2;
 Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", Twine(Value));


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -881,20 +881,18 @@
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=bti -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-BTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-PAC,CHECK-NOBTI %s
-// RUN: %clang 

[PATCH] D112421: [clang][ARM] PACBTI-M frontend support

[Ties Stuij via Phabricator via cfe-commits]

stuij added a comment.

@erichkeane : thanks so much for going through the trouble to see what the 
problem is!
I've put up a fix with your suggested change at https://reviews.llvm.org/D115141


Repository:
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[PATCH] D112427: [ARM] Implement setjmp BTI placement for PACBTI-M

[Ties Stuij via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0fbb17458a01: [ARM] Implement setjmp BTI placement for 
PACBTI-M (authored by stuij).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112427/new/

https://reviews.llvm.org/D112427

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  clang/test/Driver/arm-bti-return-twice.c
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
  llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll

Index: llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll
===
--- /dev/null
+++ llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll
@@ -0,0 +1,92 @@
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -enable-machine-outliner < %s | \
+; RUN: FileCheck %s --check-prefix=BTI
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -enable-machine-outliner -mattr=+no-bti-at-return-twice < %s | FileCheck %s --check-prefix=NOBTI
+
+; C source
+; 
+; jmp_buf buf;
+;
+; extern void h(int a, int b, int *c);
+;
+; int f(int a, int b, int c, int d) {
+;   if (setjmp(buf) != 0)
+; return -1;
+;   h(a, b, );
+;   return 2 + a * (a + b) / (c + d);
+; }
+;
+; int g(int a, int b, int c, int d) {
+;   if (setjmp(buf) != 0)
+; return -1;
+;   h(a, b, );
+;   return 1 + a * (a + b) / (c + d);
+; }
+
+@buf = global [20 x i64] zeroinitializer, align 8
+
+define i32 @f(i32 %a, i32 %b, i32 %c, i32 %d) {
+; BTI-LABEL: f:
+; BTI:   bl OUTLINED_FUNCTION_0
+; BTI-NEXT:  bti
+; NOBTI-LABEL: f:
+; NOBTI:   bl OUTLINED_FUNCTION_0
+; NOBTI-NEXT:   cbz	r0, .LBB0_2
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  %call = call i32 @setjmp(i64* getelementptr inbounds ([20 x i64], [20 x i64]* @buf, i32 0, i32 0)) #0
+  %cmp.not = icmp eq i32 %call, 0
+  br i1 %cmp.not, label %if.end, label %return
+
+if.end:   ; preds = %entry
+  call void @h(i32 %a, i32 %b, i32* nonnull %a.addr)
+  %0 = load i32, i32* %a.addr, align 4
+  %add = add nsw i32 %0, %b
+  %mul = mul nsw i32 %add, %0
+  %add1 = add nsw i32 %d, %c
+  %div = sdiv i32 %mul, %add1
+  %add2 = add nsw i32 %div, 2
+  br label %return
+
+return:   ; preds = %entry, %if.end
+  %retval.0 = phi i32 [ %add2, %if.end ], [ -1, %entry ]
+  ret i32 %retval.0
+}
+
+define i32 @g(i32 %a, i32 %b, i32 %c, i32 %d) {
+; BTI-LABEL: g:
+; BTI:   bl OUTLINED_FUNCTION_0
+; BTI-NEXT:  bti
+; NOBTI-LABEL: g:
+; NOBTI:   bl OUTLINED_FUNCTION_0
+; NOBTI-NEXT:  cbz	r0, .LBB1_2
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  %call = call i32 @setjmp(i64* getelementptr inbounds ([20 x i64], [20 x i64]* @buf, i32 0, i32 0)) #0
+  %cmp.not = icmp eq i32 %call, 0
+  br i1 %cmp.not, label %if.end, label %return
+
+if.end:   ; preds = %entry
+  call void @h(i32 %a, i32 %b, i32* nonnull %a.addr)
+  %0 = load i32, i32* %a.addr, align 4
+  %add = add nsw i32 %0, %b
+  %mul = mul nsw i32 %add, %0
+  %add1 = add nsw i32 %d, %c
+  %div = sdiv i32 %mul, %add1
+  %add2 = add nsw i32 %div, 1
+  br label %return
+
+return:   ; preds = %entry, %if.end
+  %retval.0 = phi i32 [ %add2, %if.end ], [ -1, %entry ]
+  ret i32 %retval.0
+}
+
+declare void @h(i32, i32, i32*)
+declare i32 @setjmp(i64*) #0
+
+attributes #0 = { returns_twice }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 1, !"branch-target-enforcement", i32 1}
Index: llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
@@ -0,0 +1,50 @@
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi < %s | FileCheck %s --check-prefix=BTI
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+no-bti-at-return-twice < %s | \
+; RUN: FileCheck %s --check-prefix=NOBTI
+
+; C source
+; 
+; jmp_buf buf;
+;
+; extern void bar(int x);
+;
+; int foo(int x) {
+;   if (setjmp(buf))
+; x = 0;
+;   else
+; bar(x);
+;   return x;
+; }
+
+@buf = global [20 x i64] zeroinitializer, align 8
+
+define i32 @foo(i32 %x) {
+; BTI-LABEL: foo:
+; BTI:   bl setjmp
+; BTI-NEXT:  bti
+; NOBTI-LABEL: foo:
+; NOBTI:   bl setjmp
+; NOBTI-NOT:   bti
+
+entry:
+  %call = call i32 @setjmp(i64* getelementptr inbounds ([20 x i64], [20 x i64]* @buf, i32 0, i32 0)) #0
+  %tobool.not = icmp eq i32 %call, 0
+  br i1 %tobool.not, label %if.else, label %if.end
+
+if.else:  ; preds = 

[PATCH] D115141: [ARM][clang] Add back branch protection tests

[Ties Stuij via Phabricator via cfe-commits]

stuij created this revision.
Herald added a subscriber: kristof.beyls.
stuij requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

When committing the PACBTI-M frontend support
patch (https://reviews.llvm.org/D112421), the tests in
arm-invalid-branch-protection.c were failing on certain test setups, so it was
removed to make the llvm test suite pass. The fix is to require
arm-registered-target.

This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:

https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension

The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:

https://developer.arm.com/documentation/ddi0553/latest


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115141

Files:
  clang/test/Frontend/arm-invalid-branch-protection.c


Index: clang/test/Frontend/arm-invalid-branch-protection.c
===
--- /dev/null
+++ clang/test/Frontend/arm-invalid-branch-protection.c
@@ -0,0 +1,7 @@
+// REQUIRES: arm-registered-target
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key -c 
%s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi 
-mbranch-protection=pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key 
-c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi 
-mbranch-protection=bti+pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck 
%s
+
+// CHECK: warning: invalid branch protection option 'b-key' in 
'-mbranch-protection={{[a-z+-]*}}' [-Wbranch-protection]


Index: clang/test/Frontend/arm-invalid-branch-protection.c
===
--- /dev/null
+++ clang/test/Frontend/arm-invalid-branch-protection.c
@@ -0,0 +1,7 @@
+// REQUIRES: arm-registered-target
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
+
+// CHECK: warning: invalid branch protection option 'b-key' in '-mbranch-protection={{[a-z+-]*}}' [-Wbranch-protection]
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[PATCH] D115140: [ARM][clang] Option b-key must not affect __ARM_FEATURE_PAC_DEFAULT

[Ties Stuij via Phabricator via cfe-commits]

stuij created this revision.
Herald added a subscriber: kristof.beyls.
stuij requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

When using -mbranch-protection=pac-ret+b-key, macro __ARM_FEATURE_PAC_DEFAULT
should still have the value corresponding to a-key, because b-key is only valid
for AArch64.

This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:

https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension

The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:

https://developer.arm.com/documentation/ddi0553/latest

The following people contributed to this patch:

- Victor Campos


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115140

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/test/Preprocessor/arm-target-features.c


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -881,20 +881,18 @@
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-BTI,CHECK-NOPAC %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-BTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-BTI %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
 // CHECK-NOBTI-NOT: #define __ARM_FEATURE_BTI_DEFAULT
 // CHECK-NOPAC-NOT: #define __ARM_FEATURE_PAC_DEFAULT
 // CHECK-BTI: #define __ARM_FEATURE_BTI_DEFAULT 1
 // CHECK-PAC: #define __ARM_FEATURE_PAC_DEFAULT 1
-// CHECK-PAC-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 2
 // CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
-// CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
 
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI-EXT,CHECK-NOPAC-EXT %s
 // RUN: %clang -target arm-arm-none-eabi -march=armv7-m+pacbti -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-PACBTI-EXT %s
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -911,7 +911,7 @@
 Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
 
   if (Opts.hasSignReturnAddress()) {
-unsigned Value = Opts.isSignReturnAddressWithAKey() ? 1 : 2;
+unsigned Value = 1;
 if (Opts.isSignReturnAddressScopeAll())
   Value |= 1 << 2;
 Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", Twine(Value));


Index: clang/test/Preprocessor/arm-target-features.c

[PATCH] D112421: [clang][ARM] PACBTI-M frontend support

[Ties Stuij via Phabricator via cfe-commits]

stuij added a comment.

Yes, pushed a temporary fix.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D112422: [clang][ARM] emit PACBTI-M feature defines

[Ties Stuij via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGab2611d0998c: [clang][ARM] emit PACBTI-M feature defines 
(authored by stuij).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D112422

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/test/Preprocessor/arm-target-features.c


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -877,6 +877,25 @@
 // RUN: %clang -target arm-none-none-eabi -march=armv7-m -mfpu=softvfp -x c -E 
-dM %s -o - | FileCheck --check-prefix=CHECK-SOFTVFP %s
 // CHECK-SOFTVFP-NOT: #define __ARM_FP 0x
 
+// Test Armv8.1-M PACBTI
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-BTI,CHECK-NOPAC %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-BTI %s
+// CHECK-NOBTI-NOT: #define __ARM_FEATURE_BTI_DEFAULT
+// CHECK-NOPAC-NOT: #define __ARM_FEATURE_PAC_DEFAULT
+// CHECK-BTI: #define __ARM_FEATURE_BTI_DEFAULT 1
+// CHECK-PAC: #define __ARM_FEATURE_PAC_DEFAULT 1
+// CHECK-PAC-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 2
+// CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
+// CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
+
 // == Check BFloat16 Extensions.
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.6-a+bf16 -x c -E -dM %s 
-o - 2>&1 | FileCheck -check-prefix=CHECK-BFLOAT %s
 // CHECK-BFLOAT: #define __ARM_BF16_FORMAT_ALTERNATIVE 1
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -896,6 +896,16 @@
 Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
   }
 
+  if (Opts.BranchTargetEnforcement)
+Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
+
+  if (Opts.hasSignReturnAddress()) {
+unsigned Value = Opts.isSignReturnAddressWithAKey() ? 1 : 2;
+if (Opts.isSignReturnAddressScopeAll())
+  Value |= 1 << 2;
+Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", Twine(Value));
+  }
+
   switch (ArchKind) {
   default:
 break;


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -877,6 +877,25 @@
 // RUN: %clang -target arm-none-none-eabi -march=armv7-m -mfpu=softvfp -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SOFTVFP %s
 // CHECK-SOFTVFP-NOT: #define __ARM_FP 0x
 
+// Test Armv8.1-M PACBTI
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=bti -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-BTI,CHECK-NOPAC %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-PAC,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-PAC-BKEY,CHECK-NOBTI %s
+// RUN: 

[PATCH] D112421: [clang][ARM] PACBTI-M frontend support

[Ties Stuij via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe3b2f0226bc0: [clang][ARM] PACBTI-M frontend support 
(authored by stuij).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112421/new/

https://reviews.llvm.org/D112421

Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/DiagnosticGroups.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/arm-branch-protection-attr-1.c
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/CodeGen/arm_neon_intrinsics.c
  clang/test/Driver/aarch64-security-options.c
  clang/test/Driver/arm-security-options.c
  clang/test/Frontend/arm-invalid-branch-protection.c
  clang/test/Sema/aarch64-branch-protection-attr-err.c
  clang/test/Sema/arm-branch-protection-attr-err.c
  clang/test/Sema/branch-protection-attr-err.c
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Support/TargetParser.cpp

Index: llvm/lib/Support/TargetParser.cpp
===
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -333,3 +333,51 @@
 
 } // namespace RISCV
 } // namespace llvm
+
+// Parse a branch protection specification, which has the form
+//   standard | none | [bti,pac-ret[+b-key,+leaf]*]
+// Returns true on success, with individual elements of the specification
+// returned in `PBP`. Returns false in error, with `Err` containing
+// an erroneous part of the spec.
+bool ARM::parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
+StringRef ) {
+  PBP = {"none", "a_key", false};
+  if (Spec == "none")
+return true; // defaults are ok
+
+  if (Spec == "standard") {
+PBP.Scope = "non-leaf";
+PBP.BranchTargetEnforcement = true;
+return true;
+  }
+
+  SmallVector Opts;
+  Spec.split(Opts, "+");
+  for (int I = 0, E = Opts.size(); I != E; ++I) {
+StringRef Opt = Opts[I].trim();
+if (Opt == "bti") {
+  PBP.BranchTargetEnforcement = true;
+  continue;
+}
+if (Opt == "pac-ret") {
+  PBP.Scope = "non-leaf";
+  for (; I + 1 != E; ++I) {
+StringRef PACOpt = Opts[I + 1].trim();
+if (PACOpt == "leaf")
+  PBP.Scope = "all";
+else if (PACOpt == "b-key")
+  PBP.Key = "b_key";
+else
+  break;
+  }
+  continue;
+}
+if (Opt == "")
+  Err = "";
+else
+  Err = Opt;
+return false;
+  }
+
+  return true;
+}
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -240,52 +240,4 @@
   return C.ArchID;
   }
   return ArchKind::INVALID;
-}
-
-// Parse a branch protection specification, which has the form
-//   standard | none | [bti,pac-ret[+b-key,+leaf]*]
-// Returns true on success, with individual elements of the specification
-// returned in `PBP`. Returns false in error, with `Err` containing
-// an erroneous part of the spec.
-bool AArch64::parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
-StringRef ) {
-  PBP = {"none", "a_key", false};
-  if (Spec == "none")
-return true; // defaults are ok
-
-  if (Spec == "standard") {
-PBP.Scope = "non-leaf";
-PBP.BranchTargetEnforcement = true;
-return true;
-  }
-
-  SmallVector Opts;
-  Spec.split(Opts, "+");
-  for (int I = 0, E = Opts.size(); I != E; ++I) {
-StringRef Opt = Opts[I].trim();
-if (Opt == "bti") {
-  PBP.BranchTargetEnforcement = true;
-  continue;
-}
-if (Opt == "pac-ret") {
-  PBP.Scope = "non-leaf";
-  for (; I + 1 != E; ++I) {
-StringRef PACOpt = Opts[I + 1].trim();
-if (PACOpt == "leaf")
-  PBP.Scope = "all";
-else if (PACOpt == "b-key")
-  PBP.Key = "b_key";
-else
-  break;
-  }
-  continue;
-}
-if (Opt == "")
-  Err = "";
-else
-  Err = Opt;
-return false;
-  }
-
-  return true;
-}
+}
\ No newline at end of file
Index: llvm/include/llvm/Support/TargetParser.h
===
--- llvm/include/llvm/Support/TargetParser.h
+++ llvm/include/llvm/Support/TargetParser.h
@@ -177,6 +177,18 @@
 
 } // namespace RISCV
 
+namespace ARM {
+struct ParsedBranchProtection {
+  StringRef Scope;
+  StringRef Key;
+  bool BranchTargetEnforcement;
+};
+
+bool 

[PATCH] D112421: [clang][ARM] PACBTI-M frontend support

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 390958.
stuij added a comment.

rebased and resolved merge conflict


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112421/new/

https://reviews.llvm.org/D112421

Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/DiagnosticGroups.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/arm-branch-protection-attr-1.c
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/CodeGen/arm_neon_intrinsics.c
  clang/test/Driver/aarch64-security-options.c
  clang/test/Driver/arm-security-options.c
  clang/test/Frontend/arm-invalid-branch-protection.c
  clang/test/Sema/aarch64-branch-protection-attr-err.c
  clang/test/Sema/arm-branch-protection-attr-err.c
  clang/test/Sema/branch-protection-attr-err.c
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Support/TargetParser.cpp

Index: llvm/lib/Support/TargetParser.cpp
===
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -333,3 +333,51 @@
 
 } // namespace RISCV
 } // namespace llvm
+
+// Parse a branch protection specification, which has the form
+//   standard | none | [bti,pac-ret[+b-key,+leaf]*]
+// Returns true on success, with individual elements of the specification
+// returned in `PBP`. Returns false in error, with `Err` containing
+// an erroneous part of the spec.
+bool ARM::parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
+StringRef ) {
+  PBP = {"none", "a_key", false};
+  if (Spec == "none")
+return true; // defaults are ok
+
+  if (Spec == "standard") {
+PBP.Scope = "non-leaf";
+PBP.BranchTargetEnforcement = true;
+return true;
+  }
+
+  SmallVector Opts;
+  Spec.split(Opts, "+");
+  for (int I = 0, E = Opts.size(); I != E; ++I) {
+StringRef Opt = Opts[I].trim();
+if (Opt == "bti") {
+  PBP.BranchTargetEnforcement = true;
+  continue;
+}
+if (Opt == "pac-ret") {
+  PBP.Scope = "non-leaf";
+  for (; I + 1 != E; ++I) {
+StringRef PACOpt = Opts[I + 1].trim();
+if (PACOpt == "leaf")
+  PBP.Scope = "all";
+else if (PACOpt == "b-key")
+  PBP.Key = "b_key";
+else
+  break;
+  }
+  continue;
+}
+if (Opt == "")
+  Err = "";
+else
+  Err = Opt;
+return false;
+  }
+
+  return true;
+}
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -240,52 +240,4 @@
   return C.ArchID;
   }
   return ArchKind::INVALID;
-}
-
-// Parse a branch protection specification, which has the form
-//   standard | none | [bti,pac-ret[+b-key,+leaf]*]
-// Returns true on success, with individual elements of the specification
-// returned in `PBP`. Returns false in error, with `Err` containing
-// an erroneous part of the spec.
-bool AArch64::parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
-StringRef ) {
-  PBP = {"none", "a_key", false};
-  if (Spec == "none")
-return true; // defaults are ok
-
-  if (Spec == "standard") {
-PBP.Scope = "non-leaf";
-PBP.BranchTargetEnforcement = true;
-return true;
-  }
-
-  SmallVector Opts;
-  Spec.split(Opts, "+");
-  for (int I = 0, E = Opts.size(); I != E; ++I) {
-StringRef Opt = Opts[I].trim();
-if (Opt == "bti") {
-  PBP.BranchTargetEnforcement = true;
-  continue;
-}
-if (Opt == "pac-ret") {
-  PBP.Scope = "non-leaf";
-  for (; I + 1 != E; ++I) {
-StringRef PACOpt = Opts[I + 1].trim();
-if (PACOpt == "leaf")
-  PBP.Scope = "all";
-else if (PACOpt == "b-key")
-  PBP.Key = "b_key";
-else
-  break;
-  }
-  continue;
-}
-if (Opt == "")
-  Err = "";
-else
-  Err = Opt;
-return false;
-  }
-
-  return true;
-}
+}
\ No newline at end of file
Index: llvm/include/llvm/Support/TargetParser.h
===
--- llvm/include/llvm/Support/TargetParser.h
+++ llvm/include/llvm/Support/TargetParser.h
@@ -177,6 +177,18 @@
 
 } // namespace RISCV
 
+namespace ARM {
+struct ParsedBranchProtection {
+  StringRef Scope;
+  StringRef Key;
+  bool BranchTargetEnforcement;
+};
+
+bool parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
+   StringRef );
+
+} // namespace ARM
+
 } // 

[PATCH] D112427: [ARM] Implement setjmp BTI placement for PACBTI-M

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 390633.
stuij added a comment.

slight rewording


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112427/new/

https://reviews.llvm.org/D112427

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  clang/test/Driver/arm-bti-return-twice.c
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
  llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll

Index: llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll
===
--- /dev/null
+++ llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll
@@ -0,0 +1,92 @@
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -enable-machine-outliner < %s | \
+; RUN: FileCheck %s --check-prefix=BTI
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -enable-machine-outliner -mattr=+no-bti-at-return-twice < %s | FileCheck %s --check-prefix=NOBTI
+
+; C source
+; 
+; jmp_buf buf;
+;
+; extern void h(int a, int b, int *c);
+;
+; int f(int a, int b, int c, int d) {
+;   if (setjmp(buf) != 0)
+; return -1;
+;   h(a, b, );
+;   return 2 + a * (a + b) / (c + d);
+; }
+;
+; int g(int a, int b, int c, int d) {
+;   if (setjmp(buf) != 0)
+; return -1;
+;   h(a, b, );
+;   return 1 + a * (a + b) / (c + d);
+; }
+
+@buf = global [20 x i64] zeroinitializer, align 8
+
+define i32 @f(i32 %a, i32 %b, i32 %c, i32 %d) {
+; BTI-LABEL: f:
+; BTI:   bl OUTLINED_FUNCTION_0
+; BTI-NEXT:  bti
+; NOBTI-LABEL: f:
+; NOBTI:   bl OUTLINED_FUNCTION_0
+; NOBTI-NEXT:   cbz	r0, .LBB0_2
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  %call = call i32 @setjmp(i64* getelementptr inbounds ([20 x i64], [20 x i64]* @buf, i32 0, i32 0)) #0
+  %cmp.not = icmp eq i32 %call, 0
+  br i1 %cmp.not, label %if.end, label %return
+
+if.end:   ; preds = %entry
+  call void @h(i32 %a, i32 %b, i32* nonnull %a.addr)
+  %0 = load i32, i32* %a.addr, align 4
+  %add = add nsw i32 %0, %b
+  %mul = mul nsw i32 %add, %0
+  %add1 = add nsw i32 %d, %c
+  %div = sdiv i32 %mul, %add1
+  %add2 = add nsw i32 %div, 2
+  br label %return
+
+return:   ; preds = %entry, %if.end
+  %retval.0 = phi i32 [ %add2, %if.end ], [ -1, %entry ]
+  ret i32 %retval.0
+}
+
+define i32 @g(i32 %a, i32 %b, i32 %c, i32 %d) {
+; BTI-LABEL: g:
+; BTI:   bl OUTLINED_FUNCTION_0
+; BTI-NEXT:  bti
+; NOBTI-LABEL: g:
+; NOBTI:   bl OUTLINED_FUNCTION_0
+; NOBTI-NEXT:  cbz	r0, .LBB1_2
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  %call = call i32 @setjmp(i64* getelementptr inbounds ([20 x i64], [20 x i64]* @buf, i32 0, i32 0)) #0
+  %cmp.not = icmp eq i32 %call, 0
+  br i1 %cmp.not, label %if.end, label %return
+
+if.end:   ; preds = %entry
+  call void @h(i32 %a, i32 %b, i32* nonnull %a.addr)
+  %0 = load i32, i32* %a.addr, align 4
+  %add = add nsw i32 %0, %b
+  %mul = mul nsw i32 %add, %0
+  %add1 = add nsw i32 %d, %c
+  %div = sdiv i32 %mul, %add1
+  %add2 = add nsw i32 %div, 1
+  br label %return
+
+return:   ; preds = %entry, %if.end
+  %retval.0 = phi i32 [ %add2, %if.end ], [ -1, %entry ]
+  ret i32 %retval.0
+}
+
+declare void @h(i32, i32, i32*)
+declare i32 @setjmp(i64*) #0
+
+attributes #0 = { returns_twice }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 1, !"branch-target-enforcement", i32 1}
Index: llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
@@ -0,0 +1,50 @@
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi < %s | FileCheck %s --check-prefix=BTI
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+no-bti-at-return-twice < %s | \
+; RUN: FileCheck %s --check-prefix=NOBTI
+
+; C source
+; 
+; jmp_buf buf;
+;
+; extern void bar(int x);
+;
+; int foo(int x) {
+;   if (setjmp(buf))
+; x = 0;
+;   else
+; bar(x);
+;   return x;
+; }
+
+@buf = global [20 x i64] zeroinitializer, align 8
+
+define i32 @foo(i32 %x) {
+; BTI-LABEL: foo:
+; BTI:   bl setjmp
+; BTI-NEXT:  bti
+; NOBTI-LABEL: foo:
+; NOBTI:   bl setjmp
+; NOBTI-NOT:   bti
+
+entry:
+  %call = call i32 @setjmp(i64* getelementptr inbounds ([20 x i64], [20 x i64]* @buf, i32 0, i32 0)) #0
+  %tobool.not = icmp eq i32 %call, 0
+  br i1 %tobool.not, label %if.else, label %if.end
+
+if.else:  ; preds = %entry
+  call void @bar(i32 %x)
+  br label %if.end
+
+if.end:   ; preds = %entry, %if.else
+  %x.addr.0 = 

[PATCH] D112431: [ARM][clang] Define feature test macro for the PACBTI-M extension

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 390340.
stuij added a comment.

reuploading after rebase to resolve patch apply failure


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112431/new/

https://reviews.llvm.org/D112431

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/test/Preprocessor/arm-target-features.c


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -896,6 +896,13 @@
 // CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
 // CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
 
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI-EXT,CHECK-NOPAC-EXT %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv7-m+pacbti -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-PACBTI-EXT %s
+// CHECK-NOBTI-EXT-NOT: #define __ARM_FEATURE_BTI 1
+// CHECK-NOPAC-EXT-NOT: #define __ARM_FEATURE_PAUTH 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_BTI 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_PAUTH 1
+
 // == Check BFloat16 Extensions.
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.6-a+bf16 -x c -E -dM %s 
-o - 2>&1 | FileCheck -check-prefix=CHECK-BFLOAT %s
 // CHECK-BFLOAT: #define __ARM_BF16_FORMAT_ALTERNATIVE 1
Index: clang/lib/Basic/Targets/ARM.h
===
--- clang/lib/Basic/Targets/ARM.h
+++ clang/lib/Basic/Targets/ARM.h
@@ -79,6 +79,8 @@
   unsigned DotProd : 1;
   unsigned HasMatMul : 1;
   unsigned FPRegsDisabled : 1;
+  unsigned HasPAC : 1;
+  unsigned HasBTI : 1;
 
   enum {
 LDREX_B = (1 << 0), /// byte (8-bit)
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -465,6 +465,8 @@
   HWDiv = 0;
   DotProd = 0;
   HasMatMul = 0;
+  HasPAC = 0;
+  HasBTI = 0;
   HasFloat16 = true;
   ARMCDECoprocMask = 0;
   HasBFloat16 = false;
@@ -547,6 +549,9 @@
   HasBFloat16 = true;
 } else if (Feature == "-fpregs") {
   FPRegsDisabled = true;
+} else if (Feature == "+pacbti") {
+  HasPAC = 1;
+  HasBTI = 1;
 }
   }
 
@@ -890,6 +895,12 @@
   if (HasMatMul)
 Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
 
+  if (HasPAC)
+Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
+
+  if (HasBTI)
+Builder.defineMacro("__ARM_FEATURE_BTI", "1");
+
   if (HasBFloat16) {
 Builder.defineMacro("__ARM_FEATURE_BF16", "1");
 Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -896,6 +896,13 @@
 // CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
 // CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
 
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-NOBTI-EXT,CHECK-NOPAC-EXT %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv7-m+pacbti -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-PACBTI-EXT %s
+// CHECK-NOBTI-EXT-NOT: #define __ARM_FEATURE_BTI 1
+// CHECK-NOPAC-EXT-NOT: #define __ARM_FEATURE_PAUTH 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_BTI 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_PAUTH 1
+
 // == Check BFloat16 Extensions.
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.6-a+bf16 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-BFLOAT %s
 // CHECK-BFLOAT: #define __ARM_BF16_FORMAT_ALTERNATIVE 1
Index: clang/lib/Basic/Targets/ARM.h
===
--- clang/lib/Basic/Targets/ARM.h
+++ clang/lib/Basic/Targets/ARM.h
@@ -79,6 +79,8 @@
   unsigned DotProd : 1;
   unsigned HasMatMul : 1;
   unsigned FPRegsDisabled : 1;
+  unsigned HasPAC : 1;
+  unsigned HasBTI : 1;
 
   enum {
 LDREX_B = (1 << 0), /// byte (8-bit)
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -465,6 +465,8 @@
   HWDiv = 0;
   DotProd = 0;
   HasMatMul = 0;
+  HasPAC = 0;
+  HasBTI = 0;
   HasFloat16 = true;
   ARMCDECoprocMask = 0;
   HasBFloat16 = false;
@@ -547,6 +549,9 @@
   HasBFloat16 = true;
 } else if (Feature == "-fpregs") {
   FPRegsDisabled = true;
+} else if (Feature == "+pacbti") {
+  HasPAC = 1;
+  HasBTI = 1;
 }
   }
 
@@ -890,6 +895,12 @@
   if (HasMatMul)
 Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
 
+  if (HasPAC)
+Builder.defineMacro("__ARM_FEATURE_PAUTH", 

[PATCH] D112430: [ARM][libunwind] add PACBTI-M support for libunwind

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 390333.
stuij added a comment.

uploading after rebase as per reviewer request (no changes in the patch itself)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112430/new/

https://reviews.llvm.org/D112430

Files:
  clang/lib/Headers/unwind.h
  libunwind/include/libunwind.h
  libunwind/include/unwind_arm_ehabi.h
  libunwind/src/DwarfInstructions.hpp
  libunwind/src/Registers.hpp
  libunwind/src/Unwind-EHABI.cpp
  libunwind/src/UnwindCursor.hpp
  libunwind/src/UnwindRegistersRestore.S
  libunwind/src/assembly.h

Index: libunwind/src/assembly.h
===
--- libunwind/src/assembly.h
+++ libunwind/src/assembly.h
@@ -81,7 +81,7 @@
 #define PPC64_OPD2
 #endif
 
-#if defined(__ARM_FEATURE_BTI_DEFAULT)
+#if defined(__aarch64__) && defined(__ARM_FEATURE_BTI_DEFAULT)
   .pushsection ".note.gnu.property", "a" SEPARATOR \
   .balign 8 SEPARATOR  \
   .long 4 SEPARATOR\
@@ -99,6 +99,17 @@
 #define AARCH64_BTI
 #endif
 
+#if !defined(__aarch64__)
+#ifdef __ARM_FEATURE_PAC_DEFAULT
+  .eabi_attribute Tag_PAC_extension, 2
+  .eabi_attribute Tag_PACRET_use, 1
+#endif
+#ifdef __ARM_FEATURE_BTI_DEFAULT
+  .eabi_attribute Tag_BTI_extension, 1
+  .eabi_attribute Tag_BTI_use, 1
+#endif
+#endif
+
 #define GLUE2(a, b) a ## b
 #define GLUE(a, b) GLUE2(a, b)
 #define SYMBOL_NAME(name) GLUE(__USER_LABEL_PREFIX__, name)
Index: libunwind/src/UnwindRegistersRestore.S
===
--- libunwind/src/UnwindRegistersRestore.S
+++ libunwind/src/UnwindRegistersRestore.S
@@ -660,7 +660,13 @@
   ldr sp, [lr, #52]
   ldr lr, [lr, #60]  @ restore pc into lr
 #endif
+#if defined(__ARM_FEATURE_BTI_DEFAULT) && !defined(__ARM_ARCH_ISA_ARM)
+  // 'bx' is not BTI setting when used with lr, therefore r12 is used instead
+  mov r12, lr
+  JMP(r12)
+#else
   JMP(lr)
+#endif
 
 @
 @ static void libunwind::Registers_arm::restoreVFPWithFLDMD(unw_fpreg_t* values)
Index: libunwind/src/UnwindCursor.hpp
===
--- libunwind/src/UnwindCursor.hpp
+++ libunwind/src/UnwindCursor.hpp
@@ -655,7 +655,9 @@
 #if defined(_LIBUNWIND_TARGET_X86_64)
   if (regNum >= UNW_X86_64_RAX && regNum <= UNW_X86_64_R15) return true;
 #elif defined(_LIBUNWIND_TARGET_ARM)
-  if (regNum >= UNW_ARM_R0 && regNum <= UNW_ARM_R15) return true;
+  if ((regNum >= UNW_ARM_R0 && regNum <= UNW_ARM_R15) ||
+  regNum == UNW_ARM_RA_AUTH_CODE)
+return true;
 #elif defined(_LIBUNWIND_TARGET_AARCH64)
   if (regNum >= UNW_AARCH64_X0 && regNum <= UNW_ARM64_X30) return true;
 #endif
Index: libunwind/src/Unwind-EHABI.cpp
===
--- libunwind/src/Unwind-EHABI.cpp
+++ libunwind/src/Unwind-EHABI.cpp
@@ -261,6 +261,7 @@
   size_t offset, size_t len) {
   bool wrotePC = false;
   bool finish = false;
+  bool hasReturnAddrAuthCode = false;
   while (offset < len && !finish) {
 uint8_t byte = getByte(data, offset++);
 if ((byte & 0x80) == 0) {
@@ -347,6 +348,10 @@
   break;
 }
 case 0xb4:
+  hasReturnAddrAuthCode = true;
+  _Unwind_VRS_Pop(context, _UVRSC_PSEUDO,
+  0 /* Return Address Auth Code */, _UVRSD_UINT32);
+  break;
 case 0xb5:
 case 0xb6:
 case 0xb7:
@@ -422,6 +427,16 @@
   if (!wrotePC) {
 uint32_t lr;
 _Unwind_VRS_Get(context, _UVRSC_CORE, UNW_ARM_LR, _UVRSD_UINT32, );
+#ifdef __ARM_FEATURE_PAUTH
+if (hasReturnAddrAuthCode) {
+  uint32_t sp;
+  uint32_t pac;
+  _Unwind_VRS_Get(context, _UVRSC_CORE, UNW_ARM_SP, _UVRSD_UINT32, );
+  _Unwind_VRS_Get(context, _UVRSC_PSEUDO, UNW_ARM_RA_AUTH_CODE,
+  _UVRSD_UINT32, );
+  __asm__ __volatile__("autg %0, %1, %2" : : "r"(pac), "r"(lr), "r"(sp) :);
+}
+#endif
 _Unwind_VRS_Set(context, _UVRSC_CORE, UNW_ARM_IP, _UVRSD_UINT32, );
   }
   return _URC_CONTINUE_UNWIND;
@@ -941,6 +956,15 @@
 case _UVRSC_WMMXD:
   break;
 #endif
+case _UVRSC_PSEUDO:
+  // There's only one pseudo-register, PAC, with regno == 0.
+  if (representation != _UVRSD_UINT32 || regno != 0)
+return _UVRSR_FAILED;
+  return __unw_set_reg(cursor, (unw_regnum_t)(UNW_ARM_RA_AUTH_CODE),
+   *(unw_word_t *)valuep) == UNW_ESUCCESS
+ ? _UVRSR_OK
+ : _UVRSR_FAILED;
+  break;
   }
   _LIBUNWIND_ABORT("unsupported register class");
 }
@@ -995,6 +1019,15 @@
 case _UVRSC_WMMXD:
   break;
 #endif
+case _UVRSC_PSEUDO:
+  // There's only one pseudo-register, PAC, with regno == 0.
+  if (representation != _UVRSD_UINT32 || 

[PATCH] D112422: [clang][ARM] emit PACBTI-M feature defines

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 390320.
stuij added a comment.

obeying clang-format


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112422/new/

https://reviews.llvm.org/D112422

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/test/Preprocessor/arm-target-features.c


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -877,6 +877,25 @@
 // RUN: %clang -target arm-none-none-eabi -march=armv7-m -mfpu=softvfp -x c -E 
-dM %s -o - | FileCheck --check-prefix=CHECK-SOFTVFP %s
 // CHECK-SOFTVFP-NOT: #define __ARM_FP 0x
 
+// Test Armv8.1-M PACBTI
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-BTI,CHECK-NOPAC %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main 
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck 
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-BTI %s
+// CHECK-NOBTI-NOT: #define __ARM_FEATURE_BTI_DEFAULT
+// CHECK-NOPAC-NOT: #define __ARM_FEATURE_PAC_DEFAULT
+// CHECK-BTI: #define __ARM_FEATURE_BTI_DEFAULT 1
+// CHECK-PAC: #define __ARM_FEATURE_PAC_DEFAULT 1
+// CHECK-PAC-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 2
+// CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
+// CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
+
 // == Check BFloat16 Extensions.
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.6-a+bf16 -x c -E -dM %s 
-o - 2>&1 | FileCheck -check-prefix=CHECK-BFLOAT %s
 // CHECK-BFLOAT: #define __ARM_BF16_FORMAT_ALTERNATIVE 1
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -896,6 +896,16 @@
 Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
   }
 
+  if (Opts.BranchTargetEnforcement)
+Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
+
+  if (Opts.hasSignReturnAddress()) {
+unsigned Value = Opts.isSignReturnAddressWithAKey() ? 1 : 2;
+if (Opts.isSignReturnAddressScopeAll())
+  Value |= 1 << 2;
+Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", Twine(Value));
+  }
+
   switch (ArchKind) {
   default:
 break;


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -877,6 +877,25 @@
 // RUN: %clang -target arm-none-none-eabi -march=armv7-m -mfpu=softvfp -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SOFTVFP %s
 // CHECK-SOFTVFP-NOT: #define __ARM_FP 0x
 
+// Test Armv8.1-M PACBTI
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=bti -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-BTI,CHECK-NOPAC %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-PAC,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-PAC-BKEY,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret+leaf 

[PATCH] D112421: [clang][ARM] PACBTI-M frontend support

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 390316.
stuij added a comment.

minor clang-format conformance changes


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112421/new/

https://reviews.llvm.org/D112421

Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/DiagnosticGroups.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/arm-branch-protection-attr-1.c
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/CodeGen/arm_neon_intrinsics.c
  clang/test/Driver/aarch64-security-options.c
  clang/test/Driver/arm-security-options.c
  clang/test/Frontend/arm-invalid-branch-protection.c
  clang/test/Sema/aarch64-branch-protection-attr-err.c
  clang/test/Sema/arm-branch-protection-attr-err.c
  clang/test/Sema/branch-protection-attr-err.c
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Support/TargetParser.cpp

Index: llvm/lib/Support/TargetParser.cpp
===
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -333,3 +333,51 @@
 
 } // namespace RISCV
 } // namespace llvm
+
+// Parse a branch protection specification, which has the form
+//   standard | none | [bti,pac-ret[+b-key,+leaf]*]
+// Returns true on success, with individual elements of the specification
+// returned in `PBP`. Returns false in error, with `Err` containing
+// an erroneous part of the spec.
+bool ARM::parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
+StringRef ) {
+  PBP = {"none", "a_key", false};
+  if (Spec == "none")
+return true; // defaults are ok
+
+  if (Spec == "standard") {
+PBP.Scope = "non-leaf";
+PBP.BranchTargetEnforcement = true;
+return true;
+  }
+
+  SmallVector Opts;
+  Spec.split(Opts, "+");
+  for (int I = 0, E = Opts.size(); I != E; ++I) {
+StringRef Opt = Opts[I].trim();
+if (Opt == "bti") {
+  PBP.BranchTargetEnforcement = true;
+  continue;
+}
+if (Opt == "pac-ret") {
+  PBP.Scope = "non-leaf";
+  for (; I + 1 != E; ++I) {
+StringRef PACOpt = Opts[I + 1].trim();
+if (PACOpt == "leaf")
+  PBP.Scope = "all";
+else if (PACOpt == "b-key")
+  PBP.Key = "b_key";
+else
+  break;
+  }
+  continue;
+}
+if (Opt == "")
+  Err = "";
+else
+  Err = Opt;
+return false;
+  }
+
+  return true;
+}
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -240,52 +240,4 @@
   return C.ArchID;
   }
   return ArchKind::INVALID;
-}
-
-// Parse a branch protection specification, which has the form
-//   standard | none | [bti,pac-ret[+b-key,+leaf]*]
-// Returns true on success, with individual elements of the specification
-// returned in `PBP`. Returns false in error, with `Err` containing
-// an erroneous part of the spec.
-bool AArch64::parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
-StringRef ) {
-  PBP = {"none", "a_key", false};
-  if (Spec == "none")
-return true; // defaults are ok
-
-  if (Spec == "standard") {
-PBP.Scope = "non-leaf";
-PBP.BranchTargetEnforcement = true;
-return true;
-  }
-
-  SmallVector Opts;
-  Spec.split(Opts, "+");
-  for (int I = 0, E = Opts.size(); I != E; ++I) {
-StringRef Opt = Opts[I].trim();
-if (Opt == "bti") {
-  PBP.BranchTargetEnforcement = true;
-  continue;
-}
-if (Opt == "pac-ret") {
-  PBP.Scope = "non-leaf";
-  for (; I + 1 != E; ++I) {
-StringRef PACOpt = Opts[I + 1].trim();
-if (PACOpt == "leaf")
-  PBP.Scope = "all";
-else if (PACOpt == "b-key")
-  PBP.Key = "b_key";
-else
-  break;
-  }
-  continue;
-}
-if (Opt == "")
-  Err = "";
-else
-  Err = Opt;
-return false;
-  }
-
-  return true;
-}
+}
\ No newline at end of file
Index: llvm/include/llvm/Support/TargetParser.h
===
--- llvm/include/llvm/Support/TargetParser.h
+++ llvm/include/llvm/Support/TargetParser.h
@@ -177,6 +177,18 @@
 
 } // namespace RISCV
 
+namespace ARM {
+struct ParsedBranchProtection {
+  StringRef Scope;
+  StringRef Key;
+  bool BranchTargetEnforcement;
+};
+
+bool parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
+   StringRef );
+
+} // namespace ARM
+
 } // 

[PATCH] D112420: [clang][ARM] PACBTI-M assembly support

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 390314.
stuij marked 2 inline comments as done.
stuij added a comment.

addressed review comment and clang-format suggestions


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112420/new/

https://reviews.llvm.org/D112420

Files:
  clang/test/Driver/armv8.1m.main.c
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.h
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/lib/Target/ARM/ARMPredicates.td
  llvm/lib/Target/ARM/ARMRegisterInfo.td
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/ARMSystemRegister.td
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  llvm/test/CodeGen/Thumb/high-reg-clobber.mir
  llvm/test/MC/ARM/armv8.1m-pacbti-error.s
  llvm/test/MC/ARM/armv8.1m-pacbti.s
  llvm/test/MC/ARM/implicit-it-generation-v8.s
  llvm/test/MC/Disassembler/ARM/armv8.1m-pacbti.txt

Index: llvm/test/MC/Disassembler/ARM/armv8.1m-pacbti.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/ARM/armv8.1m-pacbti.txt
@@ -0,0 +1,137 @@
+# RUN: llvm-mc -triple thumbv8.1m.main-arm-none-eabi -mattr=+pacbti -disassemble %s 2> /dev/null | FileCheck %s
+
+0x51,0xfb,0x02,0x0f
+0x5e,0xfb,0x0d,0xcf
+0xaf,0xf3,0x2d,0x80
+0x51,0xfb,0x12,0x0f
+0xaf,0xf3,0x0f,0x80
+0x61,0xfb,0x02,0xf0
+0x6e,0xfb,0x0d,0xfc
+0xaf,0xf3,0x1d,0x80
+0xaf,0xf3,0x0d,0x80
+0x80,0xf3,0x20,0x88
+0x80,0xf3,0x21,0x88
+0x80,0xf3,0x22,0x88
+0x80,0xf3,0x23,0x88
+0x80,0xf3,0x24,0x88
+0x80,0xf3,0x25,0x88
+0x80,0xf3,0x26,0x88
+0x80,0xf3,0x27,0x88
+0x80,0xf3,0xa0,0x88
+0x80,0xf3,0xa1,0x88
+0x80,0xf3,0xa2,0x88
+0x80,0xf3,0xa3,0x88
+0x80,0xf3,0xa4,0x88
+0x80,0xf3,0xa5,0x88
+0x80,0xf3,0xa6,0x88
+0x80,0xf3,0xa7,0x88
+0xef,0xf3,0x20,0x80
+0xef,0xf3,0x21,0x80
+0xef,0xf3,0x22,0x80
+0xef,0xf3,0x23,0x80
+0xef,0xf3,0x24,0x80
+0xef,0xf3,0x25,0x80
+0xef,0xf3,0x26,0x80
+0xef,0xf3,0x27,0x80
+0xef,0xf3,0xa0,0x80
+0xef,0xf3,0xa1,0x80
+0xef,0xf3,0xa2,0x80
+0xef,0xf3,0xa3,0x80
+0xef,0xf3,0xa4,0x80
+0xef,0xf3,0xa5,0x80
+0xef,0xf3,0xa6,0x80
+0xef,0xf3,0xa7,0x80
+
+# Test softfail encodings
+0xa7,0xf3,0x1d,0x80
+0xab,0xf3,0x1d,0x80
+0xad,0xf3,0x1d,0x80
+0xae,0xf3,0x1d,0x80
+0xaf,0xf3,0x1d,0x88
+0xaf,0xf3,0x1d,0xa0
+0xaf,0xf3,0x2d,0x80
+0xab,0xf3,0x2d,0x80
+0xad,0xf3,0x2d,0x80
+0xae,0xf3,0x2d,0x80
+0xaf,0xf3,0x2d,0x88
+0xaf,0xf3,0x2d,0xa0
+0xa7,0xf3,0x0f,0x80
+0xab,0xf3,0x0f,0x80
+0xad,0xf3,0x0f,0x80
+0xae,0xf3,0x0f,0x80
+0xaf,0xf3,0x0f,0x88
+0xaf,0xf3,0x0f,0xa0
+0xa7,0xf3,0x0d,0x80
+0xab,0xf3,0x0d,0x80
+0xad,0xf3,0x0d,0x80
+0xae,0xf3,0x0d,0x80
+0xaf,0xf3,0x0d,0x88
+0xaf,0xf3,0x0d,0xa0
+
+# CHECK: autg	r0, r1, r2
+# CHECK: autg r12, lr, sp
+# CHECK: aut  r12, lr, sp
+# CHECK: bxautr0, r1, r2
+# CHECK: bti
+# CHECK: pacg	r0, r1, r2
+# CHECK: pacg	r12, lr, sp
+# CHECK: pac  r12, lr, sp
+# CHECK: pacbti   r12, lr, sp
+# CHECK: msr	pac_key_p_0, r0
+# CHECK: msr	pac_key_p_1, r0
+# CHECK: msr	pac_key_p_2, r0
+# CHECK: msr	pac_key_p_3, r0
+# CHECK: msr	pac_key_u_0, r0
+# CHECK: msr	pac_key_u_1, r0
+# CHECK: msr	pac_key_u_2, r0
+# CHECK: msr	pac_key_u_3, r0
+# CHECK: msr	pac_key_p_0_ns, r0
+# CHECK: msr	pac_key_p_1_ns, r0
+# CHECK: msr	pac_key_p_2_ns, r0
+# CHECK: msr	pac_key_p_3_ns, r0
+# CHECK: msr	pac_key_u_0_ns, r0
+# CHECK: msr	pac_key_u_1_ns, r0
+# CHECK: msr	pac_key_u_2_ns, r0
+# CHECK: msr	pac_key_u_3_ns, r0
+# CHECK: mrs	r0, pac_key_p_0
+# CHECK: mrs	r0, pac_key_p_1
+# CHECK: mrs	r0, pac_key_p_2
+# CHECK: mrs	r0, pac_key_p_3
+# CHECK: mrs	r0, pac_key_u_0
+# CHECK: mrs	r0, pac_key_u_1
+# CHECK: mrs	r0, pac_key_u_2
+# CHECK: mrs	r0, pac_key_u_3
+# CHECK: mrs	r0, pac_key_p_0_ns
+# CHECK: mrs	r0, pac_key_p_1_ns
+# CHECK: mrs	r0, pac_key_p_2_ns
+# CHECK: mrs	r0, pac_key_p_3_ns
+# CHECK: mrs	r0, pac_key_u_0_ns
+# CHECK: mrs	r0, pac_key_u_1_ns
+# CHECK: mrs	r0, pac_key_u_2_ns
+# CHECK: mrs	r0, pac_key_u_3_ns
+
+# Softfail encodings
+# CHECK: pac  r12, lr, sp
+# CHECK: pac  r12, lr, sp
+# CHECK: pac  r12, lr, sp
+# CHECK: pac  r12, lr, sp
+# CHECK: pac  r12, lr, sp
+# CHECK: pac  r12, lr, sp
+# CHECK: aut  r12, lr, sp
+# CHECK: aut  r12, lr, sp
+# CHECK: aut  r12, lr, sp
+# CHECK: aut  r12, lr, sp
+# CHECK: aut  r12, lr, sp
+# CHECK: aut  r12, lr, sp
+# CHECK: bti
+# CHECK: bti
+# CHECK: bti
+# CHECK: bti
+# CHECK: bti
+# CHECK: bti
+# CHECK: pacbti   r12, lr, sp
+# CHECK: pacbti   r12, lr, sp
+# CHECK: pacbti   r12, lr, sp
+# CHECK: pacbti   r12, lr, sp
+# CHECK: pacbti   r12, lr, sp
+# CHECK: pacbti   r12, lr, sp
Index: llvm/test/MC/ARM/implicit-it-generation-v8.s
===
--- /dev/null
+++ llvm/test/MC/ARM/implicit-it-generation-v8.s
@@ -0,0 +1,9 @@
+@ RUN: llvm-mc -triple thumbv8.1m.main-arm-none-eabi -arm-implicit-it=always -mattr=+pacbti < %s -show-encoding | FileCheck %s
+
+autgeq r0, 

[PATCH] D112421: [clang][ARM] PACBTI-M frontend support

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 390021.
stuij added a comment.

addressed review comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112421/new/

https://reviews.llvm.org/D112421

Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/DiagnosticGroups.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/arm-branch-protection-attr-1.c
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/CodeGen/arm_neon_intrinsics.c
  clang/test/Driver/aarch64-security-options.c
  clang/test/Driver/arm-security-options.c
  clang/test/Frontend/arm-invalid-branch-protection.c
  clang/test/Sema/aarch64-branch-protection-attr-err.c
  clang/test/Sema/arm-branch-protection-attr-err.c
  clang/test/Sema/branch-protection-attr-err.c
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Support/TargetParser.cpp

Index: llvm/lib/Support/TargetParser.cpp
===
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -333,3 +333,51 @@
 
 } // namespace RISCV
 } // namespace llvm
+
+// Parse a branch protection specification, which has the form
+//   standard | none | [bti,pac-ret[+b-key,+leaf]*]
+// Returns true on success, with individual elements of the specification
+// returned in `PBP`. Returns false in error, with `Err` containing
+// an erroneous part of the spec.
+bool ARM::parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
+StringRef ) {
+  PBP = {"none", "a_key", false};
+  if (Spec == "none")
+return true; // defaults are ok
+
+  if (Spec == "standard") {
+PBP.Scope = "non-leaf";
+PBP.BranchTargetEnforcement = true;
+return true;
+  }
+
+  SmallVector Opts;
+  Spec.split(Opts, "+");
+  for (int I = 0, E = Opts.size(); I != E; ++I) {
+StringRef Opt = Opts[I].trim();
+if (Opt == "bti") {
+  PBP.BranchTargetEnforcement = true;
+  continue;
+}
+if (Opt == "pac-ret") {
+  PBP.Scope = "non-leaf";
+  for (; I + 1 != E; ++I) {
+StringRef PACOpt = Opts[I + 1].trim();
+if (PACOpt == "leaf")
+  PBP.Scope = "all";
+else if (PACOpt == "b-key")
+  PBP.Key = "b_key";
+else
+  break;
+  }
+  continue;
+}
+if (Opt == "")
+  Err = "";
+else
+  Err = Opt;
+return false;
+  }
+
+  return true;
+}
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -240,52 +240,4 @@
   return C.ArchID;
   }
   return ArchKind::INVALID;
-}
-
-// Parse a branch protection specification, which has the form
-//   standard | none | [bti,pac-ret[+b-key,+leaf]*]
-// Returns true on success, with individual elements of the specification
-// returned in `PBP`. Returns false in error, with `Err` containing
-// an erroneous part of the spec.
-bool AArch64::parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
-StringRef ) {
-  PBP = {"none", "a_key", false};
-  if (Spec == "none")
-return true; // defaults are ok
-
-  if (Spec == "standard") {
-PBP.Scope = "non-leaf";
-PBP.BranchTargetEnforcement = true;
-return true;
-  }
-
-  SmallVector Opts;
-  Spec.split(Opts, "+");
-  for (int I = 0, E = Opts.size(); I != E; ++I) {
-StringRef Opt = Opts[I].trim();
-if (Opt == "bti") {
-  PBP.BranchTargetEnforcement = true;
-  continue;
-}
-if (Opt == "pac-ret") {
-  PBP.Scope = "non-leaf";
-  for (; I + 1 != E; ++I) {
-StringRef PACOpt = Opts[I + 1].trim();
-if (PACOpt == "leaf")
-  PBP.Scope = "all";
-else if (PACOpt == "b-key")
-  PBP.Key = "b_key";
-else
-  break;
-  }
-  continue;
-}
-if (Opt == "")
-  Err = "";
-else
-  Err = Opt;
-return false;
-  }
-
-  return true;
-}
+}
\ No newline at end of file
Index: llvm/include/llvm/Support/TargetParser.h
===
--- llvm/include/llvm/Support/TargetParser.h
+++ llvm/include/llvm/Support/TargetParser.h
@@ -177,6 +177,18 @@
 
 } // namespace RISCV
 
+namespace ARM {
+struct ParsedBranchProtection {
+  StringRef Scope;
+  StringRef Key;
+  bool BranchTargetEnforcement;
+};
+
+bool parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
+   StringRef );
+
+} // namespace ARM
+
 } // namespace llvm
 

[PATCH] D112430: [ARM][libunwind] add PACBTI-M support for libunwind

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 389481.
stuij added a comment.

address review comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112430/new/

https://reviews.llvm.org/D112430

Files:
  clang/lib/Headers/unwind.h
  libunwind/include/libunwind.h
  libunwind/include/unwind_arm_ehabi.h
  libunwind/src/DwarfInstructions.hpp
  libunwind/src/Registers.hpp
  libunwind/src/Unwind-EHABI.cpp
  libunwind/src/UnwindCursor.hpp
  libunwind/src/UnwindRegistersRestore.S
  libunwind/src/assembly.h

Index: libunwind/src/assembly.h
===
--- libunwind/src/assembly.h
+++ libunwind/src/assembly.h
@@ -81,7 +81,7 @@
 #define PPC64_OPD2
 #endif
 
-#if defined(__ARM_FEATURE_BTI_DEFAULT)
+#if defined(__aarch64__) && defined(__ARM_FEATURE_BTI_DEFAULT)
   .pushsection ".note.gnu.property", "a" SEPARATOR \
   .balign 8 SEPARATOR  \
   .long 4 SEPARATOR\
@@ -99,6 +99,17 @@
 #define AARCH64_BTI
 #endif
 
+#if !defined(__aarch64__)
+#ifdef __ARM_FEATURE_PAC_DEFAULT
+  .eabi_attribute Tag_PAC_extension, 2
+  .eabi_attribute Tag_PACRET_use, 1
+#endif
+#ifdef __ARM_FEATURE_BTI_DEFAULT
+  .eabi_attribute Tag_BTI_extension, 1
+  .eabi_attribute Tag_BTI_use, 1
+#endif
+#endif
+
 #define GLUE2(a, b) a ## b
 #define GLUE(a, b) GLUE2(a, b)
 #define SYMBOL_NAME(name) GLUE(__USER_LABEL_PREFIX__, name)
Index: libunwind/src/UnwindRegistersRestore.S
===
--- libunwind/src/UnwindRegistersRestore.S
+++ libunwind/src/UnwindRegistersRestore.S
@@ -660,7 +660,13 @@
   ldr sp, [lr, #52]
   ldr lr, [lr, #60]  @ restore pc into lr
 #endif
+#if defined(__ARM_FEATURE_BTI_DEFAULT) && !defined(__ARM_ARCH_ISA_ARM)
+  // 'bx' is not BTI setting when used with lr, therefore r12 is used instead
+  mov r12, lr
+  JMP(r12)
+#else
   JMP(lr)
+#endif
 
 @
 @ static void libunwind::Registers_arm::restoreVFPWithFLDMD(unw_fpreg_t* values)
Index: libunwind/src/UnwindCursor.hpp
===
--- libunwind/src/UnwindCursor.hpp
+++ libunwind/src/UnwindCursor.hpp
@@ -655,7 +655,9 @@
 #if defined(_LIBUNWIND_TARGET_X86_64)
   if (regNum >= UNW_X86_64_RAX && regNum <= UNW_X86_64_R15) return true;
 #elif defined(_LIBUNWIND_TARGET_ARM)
-  if (regNum >= UNW_ARM_R0 && regNum <= UNW_ARM_R15) return true;
+  if ((regNum >= UNW_ARM_R0 && regNum <= UNW_ARM_R15) ||
+  regNum == UNW_ARM_RA_AUTH_CODE)
+return true;
 #elif defined(_LIBUNWIND_TARGET_AARCH64)
   if (regNum >= UNW_AARCH64_X0 && regNum <= UNW_ARM64_X30) return true;
 #endif
Index: libunwind/src/Unwind-EHABI.cpp
===
--- libunwind/src/Unwind-EHABI.cpp
+++ libunwind/src/Unwind-EHABI.cpp
@@ -256,6 +256,7 @@
   size_t offset, size_t len) {
   bool wrotePC = false;
   bool finish = false;
+  bool hasReturnAddrAuthCode = false;
   while (offset < len && !finish) {
 uint8_t byte = getByte(data, offset++);
 if ((byte & 0x80) == 0) {
@@ -342,6 +343,10 @@
   break;
 }
 case 0xb4:
+  hasReturnAddrAuthCode = true;
+  _Unwind_VRS_Pop(context, _UVRSC_PSEUDO,
+  0 /* Return Address Auth Code */, _UVRSD_UINT32);
+  break;
 case 0xb5:
 case 0xb6:
 case 0xb7:
@@ -417,6 +422,16 @@
   if (!wrotePC) {
 uint32_t lr;
 _Unwind_VRS_Get(context, _UVRSC_CORE, UNW_ARM_LR, _UVRSD_UINT32, );
+#ifdef __ARM_FEATURE_PAUTH
+if (hasReturnAddrAuthCode) {
+  uint32_t sp;
+  uint32_t pac;
+  _Unwind_VRS_Get(context, _UVRSC_CORE, UNW_ARM_SP, _UVRSD_UINT32, );
+  _Unwind_VRS_Get(context, _UVRSC_PSEUDO, UNW_ARM_RA_AUTH_CODE, _UVRSD_UINT32,
+  );
+  __asm__ __volatile__("autg %0, %1, %2" : : "r"(pac), "r"(lr), "r"(sp) :);
+}
+#endif
 _Unwind_VRS_Set(context, _UVRSC_CORE, UNW_ARM_IP, _UVRSD_UINT32, );
   }
   return _URC_CONTINUE_UNWIND;
@@ -927,6 +942,15 @@
 case _UVRSC_WMMXD:
   break;
 #endif
+case _UVRSC_PSEUDO:
+  // There's only one pseudo-register, PAC, with regno == 0.
+  if (representation != _UVRSD_UINT32 || regno != 0)
+return _UVRSR_FAILED;
+  return __unw_set_reg(cursor, (unw_regnum_t)(UNW_ARM_RA_AUTH_CODE),
+   *(unw_word_t *)valuep) == UNW_ESUCCESS
+ ? _UVRSR_OK
+ : _UVRSR_FAILED;
+  break;
   }
   _LIBUNWIND_ABORT("unsupported register class");
 }
@@ -981,6 +1005,15 @@
 case _UVRSC_WMMXD:
   break;
 #endif
+case _UVRSC_PSEUDO:
+  // There's only one pseudo-register, PAC, with regno == 0.
+  if (representation != _UVRSD_UINT32 || regno != 0)
+return _UVRSR_FAILED;
+  return 

[PATCH] D112427: [ARM] Implement setjmp BTI placement for PACBTI-M

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 388891.
stuij added a comment.
Herald added subscribers: cfe-commits, dang.
Herald added a project: clang.

addressed review comments, namely adding a commandline argument, 
`-mno-bti-at-return-twice`, to not place a bti instruction after a setjmp call.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112427/new/

https://reviews.llvm.org/D112427

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  clang/test/Driver/arm-bti-return-twice.c
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
  llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll

Index: llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll
===
--- /dev/null
+++ llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll
@@ -0,0 +1,92 @@
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -enable-machine-outliner < %s | \
+; RUN: FileCheck %s --check-prefix=BTI
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -enable-machine-outliner -mattr=+no-bti-at-return-twice < %s | FileCheck %s --check-prefix=NOBTI
+
+; C source
+; 
+; jmp_buf buf;
+;
+; extern void h(int a, int b, int *c);
+;
+; int f(int a, int b, int c, int d) {
+;   if (setjmp(buf) != 0)
+; return -1;
+;   h(a, b, );
+;   return 2 + a * (a + b) / (c + d);
+; }
+;
+; int g(int a, int b, int c, int d) {
+;   if (setjmp(buf) != 0)
+; return -1;
+;   h(a, b, );
+;   return 1 + a * (a + b) / (c + d);
+; }
+
+@buf = global [20 x i64] zeroinitializer, align 8
+
+define i32 @f(i32 %a, i32 %b, i32 %c, i32 %d) {
+; BTI-LABEL: f:
+; BTI:   bl OUTLINED_FUNCTION_0
+; BTI-NEXT:  bti
+; NOBTI-LABEL: f:
+; NOBTI:   bl OUTLINED_FUNCTION_0
+; NOBTI-NEXT:   cbz	r0, .LBB0_2
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  %call = call i32 @setjmp(i64* getelementptr inbounds ([20 x i64], [20 x i64]* @buf, i32 0, i32 0)) #0
+  %cmp.not = icmp eq i32 %call, 0
+  br i1 %cmp.not, label %if.end, label %return
+
+if.end:   ; preds = %entry
+  call void @h(i32 %a, i32 %b, i32* nonnull %a.addr)
+  %0 = load i32, i32* %a.addr, align 4
+  %add = add nsw i32 %0, %b
+  %mul = mul nsw i32 %add, %0
+  %add1 = add nsw i32 %d, %c
+  %div = sdiv i32 %mul, %add1
+  %add2 = add nsw i32 %div, 2
+  br label %return
+
+return:   ; preds = %entry, %if.end
+  %retval.0 = phi i32 [ %add2, %if.end ], [ -1, %entry ]
+  ret i32 %retval.0
+}
+
+define i32 @g(i32 %a, i32 %b, i32 %c, i32 %d) {
+; BTI-LABEL: g:
+; BTI:   bl OUTLINED_FUNCTION_0
+; BTI-NEXT:  bti
+; NOBTI-LABEL: g:
+; NOBTI:   bl OUTLINED_FUNCTION_0
+; NOBTI-NEXT:  cbz	r0, .LBB1_2
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  %call = call i32 @setjmp(i64* getelementptr inbounds ([20 x i64], [20 x i64]* @buf, i32 0, i32 0)) #0
+  %cmp.not = icmp eq i32 %call, 0
+  br i1 %cmp.not, label %if.end, label %return
+
+if.end:   ; preds = %entry
+  call void @h(i32 %a, i32 %b, i32* nonnull %a.addr)
+  %0 = load i32, i32* %a.addr, align 4
+  %add = add nsw i32 %0, %b
+  %mul = mul nsw i32 %add, %0
+  %add1 = add nsw i32 %d, %c
+  %div = sdiv i32 %mul, %add1
+  %add2 = add nsw i32 %div, 1
+  br label %return
+
+return:   ; preds = %entry, %if.end
+  %retval.0 = phi i32 [ %add2, %if.end ], [ -1, %entry ]
+  ret i32 %retval.0
+}
+
+declare void @h(i32, i32, i32*)
+declare i32 @setjmp(i64*) #0
+
+attributes #0 = { returns_twice }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 1, !"branch-target-enforcement", i32 1}
Index: llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
@@ -0,0 +1,50 @@
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi < %s | FileCheck %s --check-prefix=BTI
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+no-bti-at-return-twice < %s | \
+; RUN: FileCheck %s --check-prefix=NOBTI
+
+; C source
+; 
+; jmp_buf buf;
+;
+; extern void bar(int x);
+;
+; int foo(int x) {
+;   if (setjmp(buf))
+; x = 0;
+;   else
+; bar(x);
+;   return x;
+; }
+
+@buf = global [20 x i64] zeroinitializer, align 8
+
+define i32 @foo(i32 %x) {
+; BTI-LABEL: foo:
+; BTI:   bl setjmp
+; BTI-NEXT:  bti
+; NOBTI-LABEL: foo:
+; NOBTI:   bl setjmp
+; NOBTI-NOT:   bti
+
+entry:
+  %call = call i32 @setjmp(i64* getelementptr inbounds ([20 x i64], [20 x i64]* @buf, i32 0, i32 0)) #0
+  %tobool.not = icmp eq i32 %call, 0
+  br i1 %tobool.not, label %if.else, label %if.end
+

[PATCH] D112430: [ARM][libunwind] add PACBTI-M support for libunwind

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 387237.
stuij added a comment.

addressed review comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112430/new/

https://reviews.llvm.org/D112430

Files:
  clang/lib/Headers/unwind.h
  libunwind/include/libunwind.h
  libunwind/include/unwind_arm_ehabi.h
  libunwind/src/DwarfInstructions.hpp
  libunwind/src/Registers.hpp
  libunwind/src/Unwind-EHABI.cpp
  libunwind/src/UnwindCursor.hpp
  libunwind/src/UnwindRegistersRestore.S
  libunwind/src/assembly.h

Index: libunwind/src/assembly.h
===
--- libunwind/src/assembly.h
+++ libunwind/src/assembly.h
@@ -81,7 +81,7 @@
 #define PPC64_OPD2
 #endif
 
-#if defined(__ARM_FEATURE_BTI_DEFAULT)
+#if defined(__aarch64__) && defined(__ARM_FEATURE_BTI_DEFAULT)
   .pushsection ".note.gnu.property", "a" SEPARATOR \
   .balign 8 SEPARATOR  \
   .long 4 SEPARATOR\
@@ -99,6 +99,17 @@
 #define AARCH64_BTI
 #endif
 
+#if !defined(__aarch64__)
+#ifdef __ARM_FEATURE_PAC_DEFAULT
+  .eabi_attribute Tag_PAC_extension, 2
+  .eabi_attribute Tag_PACRET_use, 1
+#endif
+#ifdef __ARM_FEATURE_BTI_DEFAULT
+  .eabi_attribute Tag_BTI_extension, 1
+  .eabi_attribute Tag_BTI_use, 1
+#endif
+#endif
+
 #define GLUE2(a, b) a ## b
 #define GLUE(a, b) GLUE2(a, b)
 #define SYMBOL_NAME(name) GLUE(__USER_LABEL_PREFIX__, name)
Index: libunwind/src/UnwindRegistersRestore.S
===
--- libunwind/src/UnwindRegistersRestore.S
+++ libunwind/src/UnwindRegistersRestore.S
@@ -660,7 +660,13 @@
   ldr sp, [lr, #52]
   ldr lr, [lr, #60]  @ restore pc into lr
 #endif
+#if defined(__ARM_FEATURE_BTI_DEFAULT) && !defined(__ARM_ARCH_ISA_ARM)
+  // 'bx' is not BTI setting when used with lr, therefore r12 is used instead
+  mov r12, lr
+  JMP(r12)
+#else
   JMP(lr)
+#endif
 
 @
 @ static void libunwind::Registers_arm::restoreVFPWithFLDMD(unw_fpreg_t* values)
Index: libunwind/src/UnwindCursor.hpp
===
--- libunwind/src/UnwindCursor.hpp
+++ libunwind/src/UnwindCursor.hpp
@@ -655,7 +655,9 @@
 #if defined(_LIBUNWIND_TARGET_X86_64)
   if (regNum >= UNW_X86_64_RAX && regNum <= UNW_X86_64_R15) return true;
 #elif defined(_LIBUNWIND_TARGET_ARM)
-  if (regNum >= UNW_ARM_R0 && regNum <= UNW_ARM_R15) return true;
+  if ((regNum >= UNW_ARM_R0 && regNum <= UNW_ARM_R15) ||
+  regNum == UNW_ARM_RA_AUTH_CODE)
+return true;
 #elif defined(_LIBUNWIND_TARGET_AARCH64)
   if (regNum >= UNW_AARCH64_X0 && regNum <= UNW_ARM64_X30) return true;
 #endif
Index: libunwind/src/Unwind-EHABI.cpp
===
--- libunwind/src/Unwind-EHABI.cpp
+++ libunwind/src/Unwind-EHABI.cpp
@@ -256,6 +256,7 @@
   size_t offset, size_t len) {
   bool wrotePC = false;
   bool finish = false;
+  bool hasReturnAddrAuthCode = false;
   while (offset < len && !finish) {
 uint8_t byte = getByte(data, offset++);
 if ((byte & 0x80) == 0) {
@@ -308,7 +309,7 @@
   if (offset >= len)
 return _URC_FAILURE;
   uint8_t registers = getByte(data, offset++);
-  if (registers & 0xf0 || !registers)
+  if (registers & 0xf0)
 return _URC_FAILURE;
   _Unwind_VRS_Pop(context, _UVRSC_CORE, registers, _UVRSD_UINT32);
   break;
@@ -342,6 +343,10 @@
   break;
 }
 case 0xb4:
+  hasReturnAddrAuthCode = true;
+  _Unwind_VRS_Pop(context, _UVRSC_PSEUDO,
+  0 /* Return Address Auth Code */, _UVRSD_UINT32);
+  break;
 case 0xb5:
 case 0xb6:
 case 0xb7:
@@ -417,6 +422,16 @@
   if (!wrotePC) {
 uint32_t lr;
 _Unwind_VRS_Get(context, _UVRSC_CORE, UNW_ARM_LR, _UVRSD_UINT32, );
+#ifdef __ARM_FEATURE_PAUTH
+if (hasReturnAddrAuthCode) {
+  uint32_t sp;
+  uint32_t pac;
+  _Unwind_VRS_Get(context, _UVRSC_CORE, UNW_ARM_SP, _UVRSD_UINT32, );
+  _Unwind_VRS_Get(context, _UVRSC_PSEUDO, UNW_ARM_RA_AUTH_CODE, _UVRSD_UINT32,
+  );
+  __asm__ __volatile__("autg %0, %1, %2" : : "r"(pac), "r"(lr), "r"(sp) :);
+}
+#endif
 _Unwind_VRS_Set(context, _UVRSC_CORE, UNW_ARM_IP, _UVRSD_UINT32, );
   }
   return _URC_CONTINUE_UNWIND;
@@ -927,6 +942,15 @@
 case _UVRSC_WMMXD:
   break;
 #endif
+case _UVRSC_PSEUDO:
+  // There's only one pseudo-register, PAC, with regno == 0.
+  if (representation != _UVRSD_UINT32 || regno != 0)
+return _UVRSR_FAILED;
+  return __unw_set_reg(cursor, (unw_regnum_t)(UNW_ARM_RA_AUTH_CODE),
+   *(unw_word_t *)valuep) == UNW_ESUCCESS
+ 

[PATCH] D112431: [ARM][clang] Define feature test macro for the PACBTI-M extension

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 386195.
stuij added a comment.

addressing review comment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112431/new/

https://reviews.llvm.org/D112431

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/test/Preprocessor/arm-target-features.c


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -896,6 +896,13 @@
 // CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
 // CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
 
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-NOBTI-EXT,CHECK-NOPAC-EXT %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv7-m+pacbti -x c -E -dM %s 
-o - | FileCheck --check-prefixes=CHECK-PACBTI-EXT %s
+// CHECK-NOBTI-EXT-NOT: #define __ARM_FEATURE_BTI 1
+// CHECK-NOPAC-EXT-NOT: #define __ARM_FEATURE_PAUTH 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_BTI 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_PAUTH 1
+
 // == Check BFloat16 Extensions.
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.6-a+bf16 -x c -E -dM %s 
-o - 2>&1 | FileCheck -check-prefix=CHECK-BFLOAT %s
 // CHECK-BFLOAT: #define __ARM_BF16_FORMAT_ALTERNATIVE 1
Index: clang/lib/Basic/Targets/ARM.h
===
--- clang/lib/Basic/Targets/ARM.h
+++ clang/lib/Basic/Targets/ARM.h
@@ -79,6 +79,8 @@
   unsigned DotProd : 1;
   unsigned HasMatMul : 1;
   unsigned FPRegsDisabled : 1;
+  unsigned HasPAC : 1;
+  unsigned HasBTI : 1;
 
   enum {
 LDREX_B = (1 << 0), /// byte (8-bit)
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -465,6 +465,8 @@
   HWDiv = 0;
   DotProd = 0;
   HasMatMul = 0;
+  HasPAC = 0;
+  HasBTI = 0;
   HasFloat16 = true;
   ARMCDECoprocMask = 0;
   HasBFloat16 = false;
@@ -547,6 +549,9 @@
   HasBFloat16 = true;
 } else if (Feature == "-fpregs") {
   FPRegsDisabled = true;
+} else if (Feature == "+pacbti") {
+  HasPAC = 1;
+  HasBTI = 1;
 }
   }
 
@@ -890,6 +895,12 @@
   if (HasMatMul)
 Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
 
+  if (HasPAC)
+Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
+
+  if (HasBTI)
+Builder.defineMacro("__ARM_FEATURE_BTI", "1");
+
   if (HasBFloat16) {
 Builder.defineMacro("__ARM_FEATURE_BF16", "1");
 Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");


Index: clang/test/Preprocessor/arm-target-features.c
===
--- clang/test/Preprocessor/arm-target-features.c
+++ clang/test/Preprocessor/arm-target-features.c
@@ -896,6 +896,13 @@
 // CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
 // CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
 
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-NOBTI-EXT,CHECK-NOPAC-EXT %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv7-m+pacbti -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-PACBTI-EXT %s
+// CHECK-NOBTI-EXT-NOT: #define __ARM_FEATURE_BTI 1
+// CHECK-NOPAC-EXT-NOT: #define __ARM_FEATURE_PAUTH 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_BTI 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_PAUTH 1
+
 // == Check BFloat16 Extensions.
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.6-a+bf16 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-BFLOAT %s
 // CHECK-BFLOAT: #define __ARM_BF16_FORMAT_ALTERNATIVE 1
Index: clang/lib/Basic/Targets/ARM.h
===
--- clang/lib/Basic/Targets/ARM.h
+++ clang/lib/Basic/Targets/ARM.h
@@ -79,6 +79,8 @@
   unsigned DotProd : 1;
   unsigned HasMatMul : 1;
   unsigned FPRegsDisabled : 1;
+  unsigned HasPAC : 1;
+  unsigned HasBTI : 1;
 
   enum {
 LDREX_B = (1 << 0), /// byte (8-bit)
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -465,6 +465,8 @@
   HWDiv = 0;
   DotProd = 0;
   HasMatMul = 0;
+  HasPAC = 0;
+  HasBTI = 0;
   HasFloat16 = true;
   ARMCDECoprocMask = 0;
   HasBFloat16 = false;
@@ -547,6 +549,9 @@
   HasBFloat16 = true;
 } else if (Feature == "-fpregs") {
   FPRegsDisabled = true;
+} else if (Feature == "+pacbti") {
+  HasPAC = 1;
+  HasBTI = 1;
 }
   }
 
@@ -890,6 +895,12 @@
   if (HasMatMul)
 Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
 
+  if (HasPAC)
+Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
+
+  if (HasBTI)
+

[PATCH] D112421: [clang][ARM] PACBTI-M frontend support

[Ties Stuij via Phabricator via cfe-commits]

stuij updated this revision to Diff 384724.
stuij added a comment.

removed stray block duplicating the behaviour of CollectARMPACBTIOptions


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112421/new/

https://reviews.llvm.org/D112421

Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/DiagnosticGroups.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/arm-branch-protection-attr-1.c
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/CodeGen/arm_neon_intrinsics.c
  clang/test/Driver/aarch64-security-options.c
  clang/test/Driver/arm-security-options.c
  clang/test/Frontend/arm-invalid-branch-protection.c
  clang/test/Sema/aarch64-branch-protection-attr-err.c
  clang/test/Sema/arm-branch-protection-attr-err.c
  clang/test/Sema/branch-protection-attr-err.c
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/lib/Support/TargetParser.cpp

Index: llvm/lib/Support/TargetParser.cpp
===
--- llvm/lib/Support/TargetParser.cpp
+++ llvm/lib/Support/TargetParser.cpp
@@ -333,3 +333,51 @@
 
 } // namespace RISCV
 } // namespace llvm
+
+// Parse a branch protection specification, which has the form
+//   standard | none | [bti,pac-ret[+b-key,+leaf]*]
+// Returns true on success, with individual elements of the specification
+// returned in `PBP`. Returns false in error, with `Err` containing
+// an erroneous part of the spec.
+bool ARM::parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
+StringRef ) {
+  PBP = {"none", "a_key", false};
+  if (Spec == "none")
+return true; // defaults are ok
+
+  if (Spec == "standard") {
+PBP.Scope = "non-leaf";
+PBP.BranchTargetEnforcement = true;
+return true;
+  }
+
+  SmallVector Opts;
+  Spec.split(Opts, "+");
+  for (int I = 0, E = Opts.size(); I != E; ++I) {
+StringRef Opt = Opts[I].trim();
+if (Opt == "bti") {
+  PBP.BranchTargetEnforcement = true;
+  continue;
+}
+if (Opt == "pac-ret") {
+  PBP.Scope = "non-leaf";
+  for (; I + 1 != E; ++I) {
+StringRef PACOpt = Opts[I + 1].trim();
+if (PACOpt == "leaf")
+  PBP.Scope = "all";
+else if (PACOpt == "b-key")
+  PBP.Key = "b_key";
+else
+  break;
+  }
+  continue;
+}
+if (Opt == "")
+  Err = "";
+else
+  Err = Opt;
+return false;
+  }
+
+  return true;
+}
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -240,52 +240,4 @@
   return C.ArchID;
   }
   return ArchKind::INVALID;
-}
-
-// Parse a branch protection specification, which has the form
-//   standard | none | [bti,pac-ret[+b-key,+leaf]*]
-// Returns true on success, with individual elements of the specification
-// returned in `PBP`. Returns false in error, with `Err` containing
-// an erroneous part of the spec.
-bool AArch64::parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
-StringRef ) {
-  PBP = {"none", "a_key", false};
-  if (Spec == "none")
-return true; // defaults are ok
-
-  if (Spec == "standard") {
-PBP.Scope = "non-leaf";
-PBP.BranchTargetEnforcement = true;
-return true;
-  }
-
-  SmallVector Opts;
-  Spec.split(Opts, "+");
-  for (int I = 0, E = Opts.size(); I != E; ++I) {
-StringRef Opt = Opts[I].trim();
-if (Opt == "bti") {
-  PBP.BranchTargetEnforcement = true;
-  continue;
-}
-if (Opt == "pac-ret") {
-  PBP.Scope = "non-leaf";
-  for (; I + 1 != E; ++I) {
-StringRef PACOpt = Opts[I + 1].trim();
-if (PACOpt == "leaf")
-  PBP.Scope = "all";
-else if (PACOpt == "b-key")
-  PBP.Key = "b_key";
-else
-  break;
-  }
-  continue;
-}
-if (Opt == "")
-  Err = "";
-else
-  Err = Opt;
-return false;
-  }
-
-  return true;
-}
+}
\ No newline at end of file
Index: llvm/include/llvm/Support/TargetParser.h
===
--- llvm/include/llvm/Support/TargetParser.h
+++ llvm/include/llvm/Support/TargetParser.h
@@ -177,6 +177,18 @@
 
 } // namespace RISCV
 
+namespace ARM {
+struct ParsedBranchProtection {
+  StringRef Scope;
+  StringRef Key;
+  bool BranchTargetEnforcement;
+};
+
+bool parseBranchProtection(StringRef Spec, ParsedBranchProtection ,
+   StringRef 

[PATCH] D112420: [clang][ARM] PACBTI-M assembly support

[Ties Stuij via Phabricator via cfe-commits]

stuij marked 6 inline comments as done.
stuij added a comment.

A slight amendment to the description of the just uploaded patch amendment: 
PACG has also been made conditional.




Comment at: llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp:6441
+  Mnemonic == "csetm" ||
+  Mnemonic == "autg"  || Mnemonic == "aut"   ||
+  Mnemonic == "bxaut" || Mnemonic == "pacg"  || Mnemonic == "pac" ||

ostannard wrote:
> PACG, AUTG and BXAUT can be conditional, so shouldn't be in this list.
Thanks. Besides removing these from this list and the one below, I've added a 
predicate operator to actually make them conditional. The description of the 
patch amend didn't mention PACG, but it too has been made conditional.



Comment at: llvm/test/MC/ARM/armv8.1m-pacbti-error.s:3
+
+// CHECK: error: invalid instruction
+pac r0, r1, r2

ostannard wrote:
> We should also test the cases where PACG/AUTG/BXAUT cannot use PC/SP.
Thanks. Adding extra testcases uncovered a number of cases where the changes 
didn't match the spec. This should now be resolved.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112420/new/

https://reviews.llvm.org/D112420

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