Re: gEDA-user: Error message when creating a SUBCKT
To solved the thread. With custom symbol with power pin, the netlist generated are ok. Thanks for all your help. Ludovic On Sun, Aug 17, 2008 at 8:44 AM, Ludovic SMADJA [EMAIL PROTECTED]wrote: ok, So if I have correctly understood, the symbol provided with gEDA are designed to do PCB, not simulation. In case of simulation, it's simpler to have symbol with all pins (power included), in to order to netlist correctly. I will check with a custom symbol with power pin and I reply to you about the result. Thanks for your help. Ludovic On Sun, Aug 17, 2008 at 2:26 AM, Peter Clifton [EMAIL PROTECTED] wrote: On Sat, 2008-08-16 at 15:59 -0400, John Doty wrote: On Aug 16, 2008, at 3:32 PM, John Doty wrote: Hmm, I wonder if the problem is the hidden power pins, I note that it there is no mechanism to tell gnetlist what subcircuit pin a hidden net should attach to. You are correct. Remove the hidden power pins, and the warnings go away. A little debugging code I added to gnetlist confirmed that these pins are being passed as unknown into the C function behind get-nets. The netlist output is correct (by some definition of correct) though, in both cases. However.. perhaps your model for that gate wants power pins passing to it... Best make up a custom symbol. Again, it is strange to use a symbol designed for slotted printed circuit layout in a SPICE simulation. +1. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Ludovic SMADJA -- Ludovic SMADJA ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
ok, So if I have correctly understood, the symbol provided with gEDA are designed to do PCB, not simulation. In case of simulation, it's simpler to have symbol with all pins (power included), in to order to netlist correctly. I will check with a custom symbol with power pin and I reply to you about the result. Thanks for your help. Ludovic On Sun, Aug 17, 2008 at 2:26 AM, Peter Clifton [EMAIL PROTECTED] wrote: On Sat, 2008-08-16 at 15:59 -0400, John Doty wrote: On Aug 16, 2008, at 3:32 PM, John Doty wrote: Hmm, I wonder if the problem is the hidden power pins, I note that it there is no mechanism to tell gnetlist what subcircuit pin a hidden net should attach to. You are correct. Remove the hidden power pins, and the warnings go away. A little debugging code I added to gnetlist confirmed that these pins are being passed as unknown into the C function behind get-nets. The netlist output is correct (by some definition of correct) though, in both cases. However.. perhaps your model for that gate wants power pins passing to it... Best make up a custom symbol. Again, it is strange to use a symbol designed for slotted printed circuit layout in a SPICE simulation. +1. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Ludovic SMADJA ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
Yes I've followed the tutorial you linked, gsymcheck give no errors for the sym I use (generic 7408 sym provided with geda) for drc2 check, I've already done it and the result is some warning : WARNING: Pin(s) with pintype 'output': U2:6 are connected by net 'unnamed_net11' to pin(s) with pintype 'input/output': P6:1 WARNING: Unused slot 3 of uref U2 WARNING: Unused slot 4 of uref U2 I'm really lost and cannot found what's wrong in my schematic. Regards, Ludovic I've check the pinseq and pinnumber but I've not seen something wrong. On Fri, Aug 15, 2008 at 7:25 PM, John Doty [EMAIL PROTECTED] wrote: On Aug 14, 2008, at 2:28 AM, Ludovic SMADJA wrote: I'm creating a SUBCKT to simulate a 74191 counter. I use the schema provided in the datasheet and in this schema, there is an AND ic whith 5 entries. Have you looked at: www.brorson.com/gEDA/SPICE/intro.html Invalid wanted_pin passed to get-nets [unknown] A common reason for this message is components with duplicated refdes and pin numbers. found pin with no pinseq attribute. Ignoring. . . . Pins *must* have pinseq attributes for spice-sdb. Have you checked your symbols with gsymcheck -vv? Have you used gnetlist -g drc2 to check your schematic? Pure digital schematics are what it's designed for. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Ludovic SMADJA ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
Note I've not precised in my precedent post, I use generic schematic with slot (without slot, it's working well, and custom symbol with slot is working well). Ludovic On Sat, Aug 16, 2008 at 8:55 AM, Ludovic SMADJA [EMAIL PROTECTED]wrote: Yes I've followed the tutorial you linked, gsymcheck give no errors for the sym I use (generic 7408 sym provided with geda) for drc2 check, I've already done it and the result is some warning : WARNING: Pin(s) with pintype 'output': U2:6 are connected by net 'unnamed_net11' to pin(s) with pintype 'input/output': P6:1 WARNING: Unused slot 3 of uref U2 WARNING: Unused slot 4 of uref U2 I'm really lost and cannot found what's wrong in my schematic. Regards, Ludovic I've check the pinseq and pinnumber but I've not seen something wrong. On Fri, Aug 15, 2008 at 7:25 PM, John Doty [EMAIL PROTECTED] wrote: On Aug 14, 2008, at 2:28 AM, Ludovic SMADJA wrote: I'm creating a SUBCKT to simulate a 74191 counter. I use the schema provided in the datasheet and in this schema, there is an AND ic whith 5 entries. Have you looked at: www.brorson.com/gEDA/SPICE/intro.html Invalid wanted_pin passed to get-nets [unknown] A common reason for this message is components with duplicated refdes and pin numbers. found pin with no pinseq attribute. Ignoring. . . . Pins *must* have pinseq attributes for spice-sdb. Have you checked your symbols with gsymcheck -vv? Have you used gnetlist -g drc2 to check your schematic? Pure digital schematics are what it's designed for. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Ludovic SMADJA -- Ludovic SMADJA ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Error message when creating a SUBCKT
About the unused slots, it doesn't seems to be the problem. When I add the 2 unused slots to my schematics and link theirs input pins to ground and output pin to NC symbol, drc2 removes the warning but the spice-sdb give me more Invalid wanted_pin passed to get-nets [unknown] I've already use slots in another circuit without any problem. Ludovic On Sat, Aug 16, 2008 at 4:51 PM, Peter Clifton [EMAIL PROTECTED] wrote: On Sat, 2008-08-16 at 09:26 -0400, John Doty wrote: On Aug 16, 2008, at 2:55 AM, Ludovic SMADJA wrote: WARNING: Unused slot 3 of uref U2 WARNING: Unused slot 4 of uref U2 I believe that unused slots are poison to the way spice-sdb works. For a slotted component, it expects that the model will implement all slots. Since pins are positional in SPICE netlists, it needs to list every pin on the component. Perhaps for the spice backend, but IIRC, spice-sdb renames each slot, so U2 becomes. U2.1 U2.2 U2.3 U2.4 e.g. 4 components instantiated. I might be wrong in the fine-print though. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Ludovic SMADJA ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Error message when creating a SUBCKT
Hi, I'm creating a SUBCKT to simulate a 74191 counter. I use the schema provided in the datasheet and in this schema, there is an AND ic whith 5 entries. Because the IC doesn't exist in geda library, I create it. But when I want to generate the netlist file (.cir) to link the circuit and the symbol gnetlist generate some errors. I've activated debug mode but the given information is not very useful. Here's my files and the command [EMAIL PROTECTED] commandeServo]$ gnetlist -g spice-sdb -o test.cir multipleAND.sch Command line passed = gnetlist -g spice-sdb -o test.cir multipleAND.sch gEDA/gnetlist version 1.4.0.20080127 Loading schematic [/opt/data/electronique/projets/commandeServo/multipleAND.sch] Using SPICE backend by SDB -- Version of 4.28.2007 schematic-type = .SUBCKT multipleAND Invalid wanted_pin passed to get-nets [unknown] Invalid wanted_pin passed to get-nets [unknown] Invalid wanted_pin passed to get-nets [unknown] Invalid wanted_pin passed to get-nets [unknown] Invalid wanted_pin passed to get-nets [unknown] Invalid wanted_pin passed to get-nets [unknown] Invalid wanted_pin passed to get-nets [unknown] Invalid wanted_pin passed to get-nets [unknown] Invalid wanted_pin passed to get-nets [unknown] Invalid wanted_pin passed to get-nets [unknown] Invalid wanted_pin passed to get-nets [unknown] Invalid wanted_pin passed to get-nets [unknown] Could you indicate me what I'm doing wrong ? regards, Ludovic debug messages : [EMAIL PROTECTED] commandeServo]$ gnetlist -v -g spice-sdb -o test.cir multipleAND.sch Command line passed = gnetlist -v -g spice-sdb -o test.cir multipleAND.sch gEDA/gnetlist version 1.4.0.20080127 gEDA/gnetlist comes with ABSOLUTELY NO WARRANTY; see COPYING for more details. This is free software, and you are welcome to redistribute it under certain conditions; please see the COPYING file for more details. Remember to check that your schematic has no errors using the drc2 backend. You can do it running 'gnetlist -g drc2 your_schematic.sch -o drc_output.txt' and seeing the contents of the file drc_output.txt. Loading schematic [/opt/data/electronique/projets/commandeServo/multipleAND.sch] -- Verbose mode legend n : Found net C : Found component (staring to traverse component) p : Found pin (starting to traverse pin / or examining pin) P : Found end pin connection (end of this net) R : Starting to rename a net v : Found source attribute, traversing down ^ : Finished underlying source, going back up u : Found a refdes which needs to be demangle U : Found a connected_to refdes which needs to be demangle -- - Starting internal netlist creation CpnnPpnnPpnP CpnnnPpnPpnP CpnnPpnPpnP CpnnnPpnnPpnnnP CpnnPpnPpnnP CpnPpnnnPpnnP Cp nnP CpnP C CpnP CpnP CpnP CpnP CpnP CpnP DONE - Staring post processing - Naming nets: pnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpn DONE - Renaming nets: DONE - Resolving hierarchy: DONE DONE - Staring post processing - Naming nets of graphical objects: DONE Internal netlist representation: component U1.1 pin 3 (Y) 1 U1.1 3 [149] U1.4 12 [2208] pin 1 (A) Vcc U1.1 1 [204] pin 2 (B) 2 U1.1 2 [223] P1 1 [4674] pin 14 () Vcc U1.1 14 [1] pin 7 () GND U1.1 7 [1] component U1.2 pin 6 (Y) 3 U1.2 6 [1159] U1.4 13 [2223] pin 4 (A) 4 U1.2 4 [1198] P2 1 [5116] pin 5 (B) 5 U1.2 5 [1213] P3 1 [5559] pin 14 () Vcc U1.2 14 [1063] pin 7 () GND U1.2 7 [1063] component U1.3 pin 8 (Y) 6 U1.3 8 [1651] U2.1 2 [2700] pin 9 (A) 7 U1.3 9 [1690] P4 1 [6012] pin 10 (B) 8 U1.3 10 [1705] P5 1 [6441] pin 14 () Vcc U1.3 14 [1555] pin 7 () GND U1.3 7 [1555] component U1.4 pin 11 (Y) 9 U1.4 11 [2169] U2.2 4 [3158] pin 12 (A) 1 U1.4 12 [2208] U1.1 3 [149] pin 13 (B) 3 U1.4 13 [2223] U1.2 6 [1159] pin 14 () Vcc U1.4 14 [2073] pin 7 () GND U1.4 7 [2073] component U2.1 pin 3 (Y) 10 U2.1 3 [2646] U2.2 5 [3173] pin 1 (A) Vcc U2.1 1 [2685] pin 2 (B) 6 U2.1 2 [2700] U1.3 8 [1651] pin 14 () Vcc U2.1 14 [2550] pin 7 () GND U2.1 7 [2550] component U2.2 pin 6 (Y) 11 U2.2 6 [3119] P6 1 [6886] pin 4 (A) 9 U2.2 4 [3158] U1.4 11 [2169] pin 5 (B) 10 U2.2 5 [3173] U2.1 3 [2646] pin 14 () Vcc U2.2 14 [3023] pin 7 () GND U2.2 7 [3023] component SPECIAL pin 1 (1) Null net name U1.1 1 [204] component SPECIAL pin 1 (1) Null net name U2.1 1 [2685] component A1 component P1 pin 1 (1) 2 P1 1 [4674] U1.1 2 [223] component P2
Re: gEDA-user: some problem about gnetlist and subsckt
thanks for the history .
Is there a new tutorial with gnucap use, somewhere ?
Ludovic
On Fri, Aug 8, 2008 at 9:04 AM, Ludovic SMADJA [EMAIL PROTECTED]wrote:
Hi, everyone
In order to create and simulate a quite complex schema, I've first tried to
follow the tutorial (http://www.brorson.com/gEDA/SPICE/intro.html) to
create a simple subckt with gschem and simulate it.
The subschema is a simple filter with 1 resistor and 1 capacitor. I've
integrated the schema in an upper one with one voltage source and a charge
resistor.
When I generate the netlist, gnetlist doesn't complains about anything but
the generated netlist is incorrect, the subckt is created but with the full
schema, not only the subschema :
here's my files and the command I used. Could you indicate what's I've do
wrong, I've tried all the past day to generate a correct netlist and I can't
see what's the problem ?
Regards,
Ludovic SMADJA
Commands :
gnetlist -g spice-sdb -o filtre.cir filtre.sch
gnetlist -g spice-sdb -o testFiltre.cir testFiltre.sch
**
[EMAIL PROTECTED] test]$ cat filtre.sch
v 20071231 1
C 4 4 0 0 0 title-B.sym
C 46600 46300 1 0 0 resistor-2.sym
{
T 47000 46650 5 10 0 0 0 0 1
device=RESISTOR
T 46800 46600 5 10 1 1 0 0 1
refdes=R1
T 46600 46300 5 10 1 0 0 0 1
value=100k
}
C 48100 45300 1 90 0 capacitor-1.sym
{
T 47400 45500 5 10 0 0 90 0 1
device=CAPACITOR
T 47600 45500 5 10 1 1 90 0 1
refdes=C1
T 47200 45500 5 10 0 0 90 0 1
symversion=0.1
T 48100 45300 5 10 1 0 0 0 1
value=1Uf
}
C 44100 47600 1 0 0 spice-subcircuit-LL-1.sym
{
T 44200 47900 5 10 0 1 0 0 1
device=spice-subcircuit-LL
T 44200 48000 5 10 1 1 0 0 1
refdes=A1
T 44200 47700 5 10 1 1 0 0 1
model-name=filtre_model
T 44100 47600 5 10 1 0 0 0 1
value=filtre_model
}
C 46100 46700 1 180 0 spice-subcircuit-IO-1.sym
{
T 45200 46300 5 10 0 1 180 0 1
device=spice-IO
T 45250 46450 5 10 1 1 180 0 1
refdes=P1
T 46100 46700 5 10 1 0 0 0 1
pinseq=1
T 46100 46700 5 10 1 0 0 0 1
pinlabel=IN
T 46100 46700 5 10 1 0 0 0 1
value=IN
}
N 45900 46400 46600 46400 4
N 47900 46400 47900 46200 4
N 47500 46400 48600 46400 4
N 47900 45300 47900 44900 4
N 45900 44900 48700 44900 4
C 46100 45200 1 180 0 spice-subcircuit-IO-1.sym
{
T 45200 44800 5 10 0 1 180 0 1
device=spice-IO
T 45250 44950 5 10 1 1 180 0 1
refdes=P2
T 46100 45200 5 10 1 0 0 0 1
pinseq=2
T 46100 45200 5 10 1 0 0 0 1
pinlabel=GND1
T 46100 45200 5 10 1 0 0 0 1
value=GND1
}
C 48400 46100 1 0 0 spice-subcircuit-IO-1.sym
{
T 49300 46500 5 10 0 1 0 0 1
device=spice-IO
T 49250 46350 5 10 1 1 0 0 1
refdes=P3
T 48400 46100 5 10 1 0 0 0 1
pinseq=3
T 48400 46100 5 10 1 0 0 0 1
pinlabel=OUT
T 48400 46100 5 10 1 0 0 0 1
value=OUT
}
C 48500 44600 1 0 0 spice-subcircuit-IO-1.sym
{
T 49400 45000 5 10 0 1 0 0 1
device=spice-IO
T 49350 44850 5 10 1 1 0 0 1
refdes=P4
T 48500 44600 5 10 1 0 0 0 1
pinseq=4
T 48500 44600 5 10 1 0 0 0 1
pinlabel=GND2
T 48500 44600 5 10 1 0 0 0 1
value=GND2
}
[EMAIL PROTECTED] test]$ cat filtre.sym
v 20071231 1
B 300 300 2800 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 3100 1600 9 10 0 0 0 0 1
device=filtre_model
T 1700 400 9 10 1 1 0 3 1
refdes=X?
T 1700 800 9 10 1 1 0 3 1
Filtre
P 0 1100 300 1100 1 0 0
{
T 350 1100 9 10 1 1 0 1 1
pinlabel=P1
T 200 1150 5 8 1 1 0 6 1
pinnumber=1
T 200 1150 5 8 0 1 0 6 1
pinseq=1
T 0 1100 5 10 1 0 0 0 1
refdes=IN
}
P 0 700 300 700 1 0 0
{
T 350 700 9 10 1 1 0 1 1
pinlabel=P2
T 200 750 5 8 1 1 0 6 1
pinnumber=2
T 200 750 5 8 0 1 0 6 1
pinseq=2
T 100 700 5 10 1 0 0 0 1
refdes=GND1
}
P 3400 1100 3100 1100 1 0 0
{
T 3050 1100 9 10 1 1 0 7 1
pinlabel=P3
T 3200 1150 5 8 1 1 0 0 1
pinnumber=3
T 3200 1150 5 8 0 1 0 0 1
pinseq=3
T 3400 1100 5 10 1 0 0 0 1
refdes=OUT
}
P 3400 700 3100 700 1 0 0
{
T 3050 700 9 10 1 1 0 7 1
pinlabel=P4
T 3200 750 5 8 1 1 0 0 1
pinnumber=4
T 3200 750 5 8 0 1 0 0 1
pinseq=4
T 3400 700 5 10 1 0 0 0 1
refdes=GND2
}
T 1700 400 8 10 0 1 0 0 1
source=filtre.sch
**
[EMAIL PROTECTED] test]$ cat testFiltre.sch
v 20071231 1
C 4 4 0 0 0 title-B.sym
C 47100 46700 1 0 0 filtre.sym
{
T 50200 48300 5 10 0 0 0 0 1
device=filtre_model
T 48800 47100 5 10 1 1 0 3 1
refdes=X1
T 48100 46500 5 10 1 0 0 0 1
file=filtre.cir
T 47100 46700 5 10 1 0 0 0 1
model-name=filtre_model
}
C 51900 47100 1 90 0 resistor-2.sym
{
T 51550 47500 5 10 0 0 90 0 1
device=RESISTOR
T 51600 47300 5 10 1 1 90 0 1
refdes=RTest
}
C 46200 47200 1 90 0 voltage-1.sym
{
T 45700 47300 5 10 0 0 90 0 1
device=VOLTAGE_SOURCE
T 45700 47500 5 10 1 1 90 0 1
refdes=V1
}
N 46000 48100 47100 48100 4
N 47100 48100 47100 47800 4
N 46000 47200 47100 47200 4
N 47100 47200 47100 47400 4
N 50500 47800 50500 48400 4
N 50500 48400 51800 48400 4
{
T 50500 48400 5 10 1 0 0 0 1
gEDA-user: some problem about gnetlist and subsckt
Hi, everyone
In order to create and simulate a quite complex schema, I've first tried to
follow the tutorial (http://www.brorson.com/gEDA/SPICE/intro.html) to create
a simple subckt with gschem and simulate it.
The subschema is a simple filter with 1 resistor and 1 capacitor. I've
integrated the schema in an upper one with one voltage source and a charge
resistor.
When I generate the netlist, gnetlist doesn't complains about anything but
the generated netlist is incorrect, the subckt is created but with the full
schema, not only the subschema :
here's my files and the command I used. Could you indicate what's I've do
wrong, I've tried all the past day to generate a correct netlist and I can't
see what's the problem ?
Regards,
Ludovic SMADJA
Commands :
gnetlist -g spice-sdb -o filtre.cir filtre.sch
gnetlist -g spice-sdb -o testFiltre.cir testFiltre.sch
**
[EMAIL PROTECTED] test]$ cat filtre.sch
v 20071231 1
C 4 4 0 0 0 title-B.sym
C 46600 46300 1 0 0 resistor-2.sym
{
T 47000 46650 5 10 0 0 0 0 1
device=RESISTOR
T 46800 46600 5 10 1 1 0 0 1
refdes=R1
T 46600 46300 5 10 1 0 0 0 1
value=100k
}
C 48100 45300 1 90 0 capacitor-1.sym
{
T 47400 45500 5 10 0 0 90 0 1
device=CAPACITOR
T 47600 45500 5 10 1 1 90 0 1
refdes=C1
T 47200 45500 5 10 0 0 90 0 1
symversion=0.1
T 48100 45300 5 10 1 0 0 0 1
value=1Uf
}
C 44100 47600 1 0 0 spice-subcircuit-LL-1.sym
{
T 44200 47900 5 10 0 1 0 0 1
device=spice-subcircuit-LL
T 44200 48000 5 10 1 1 0 0 1
refdes=A1
T 44200 47700 5 10 1 1 0 0 1
model-name=filtre_model
T 44100 47600 5 10 1 0 0 0 1
value=filtre_model
}
C 46100 46700 1 180 0 spice-subcircuit-IO-1.sym
{
T 45200 46300 5 10 0 1 180 0 1
device=spice-IO
T 45250 46450 5 10 1 1 180 0 1
refdes=P1
T 46100 46700 5 10 1 0 0 0 1
pinseq=1
T 46100 46700 5 10 1 0 0 0 1
pinlabel=IN
T 46100 46700 5 10 1 0 0 0 1
value=IN
}
N 45900 46400 46600 46400 4
N 47900 46400 47900 46200 4
N 47500 46400 48600 46400 4
N 47900 45300 47900 44900 4
N 45900 44900 48700 44900 4
C 46100 45200 1 180 0 spice-subcircuit-IO-1.sym
{
T 45200 44800 5 10 0 1 180 0 1
device=spice-IO
T 45250 44950 5 10 1 1 180 0 1
refdes=P2
T 46100 45200 5 10 1 0 0 0 1
pinseq=2
T 46100 45200 5 10 1 0 0 0 1
pinlabel=GND1
T 46100 45200 5 10 1 0 0 0 1
value=GND1
}
C 48400 46100 1 0 0 spice-subcircuit-IO-1.sym
{
T 49300 46500 5 10 0 1 0 0 1
device=spice-IO
T 49250 46350 5 10 1 1 0 0 1
refdes=P3
T 48400 46100 5 10 1 0 0 0 1
pinseq=3
T 48400 46100 5 10 1 0 0 0 1
pinlabel=OUT
T 48400 46100 5 10 1 0 0 0 1
value=OUT
}
C 48500 44600 1 0 0 spice-subcircuit-IO-1.sym
{
T 49400 45000 5 10 0 1 0 0 1
device=spice-IO
T 49350 44850 5 10 1 1 0 0 1
refdes=P4
T 48500 44600 5 10 1 0 0 0 1
pinseq=4
T 48500 44600 5 10 1 0 0 0 1
pinlabel=GND2
T 48500 44600 5 10 1 0 0 0 1
value=GND2
}
[EMAIL PROTECTED] test]$ cat filtre.sym
v 20071231 1
B 300 300 2800 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 3100 1600 9 10 0 0 0 0 1
device=filtre_model
T 1700 400 9 10 1 1 0 3 1
refdes=X?
T 1700 800 9 10 1 1 0 3 1
Filtre
P 0 1100 300 1100 1 0 0
{
T 350 1100 9 10 1 1 0 1 1
pinlabel=P1
T 200 1150 5 8 1 1 0 6 1
pinnumber=1
T 200 1150 5 8 0 1 0 6 1
pinseq=1
T 0 1100 5 10 1 0 0 0 1
refdes=IN
}
P 0 700 300 700 1 0 0
{
T 350 700 9 10 1 1 0 1 1
pinlabel=P2
T 200 750 5 8 1 1 0 6 1
pinnumber=2
T 200 750 5 8 0 1 0 6 1
pinseq=2
T 100 700 5 10 1 0 0 0 1
refdes=GND1
}
P 3400 1100 3100 1100 1 0 0
{
T 3050 1100 9 10 1 1 0 7 1
pinlabel=P3
T 3200 1150 5 8 1 1 0 0 1
pinnumber=3
T 3200 1150 5 8 0 1 0 0 1
pinseq=3
T 3400 1100 5 10 1 0 0 0 1
refdes=OUT
}
P 3400 700 3100 700 1 0 0
{
T 3050 700 9 10 1 1 0 7 1
pinlabel=P4
T 3200 750 5 8 1 1 0 0 1
pinnumber=4
T 3200 750 5 8 0 1 0 0 1
pinseq=4
T 3400 700 5 10 1 0 0 0 1
refdes=GND2
}
T 1700 400 8 10 0 1 0 0 1
source=filtre.sch
**
[EMAIL PROTECTED] test]$ cat testFiltre.sch
v 20071231 1
C 4 4 0 0 0 title-B.sym
C 47100 46700 1 0 0 filtre.sym
{
T 50200 48300 5 10 0 0 0 0 1
device=filtre_model
T 48800 47100 5 10 1 1 0 3 1
refdes=X1
T 48100 46500 5 10 1 0 0 0 1
file=filtre.cir
T 47100 46700 5 10 1 0 0 0 1
model-name=filtre_model
}
C 51900 47100 1 90 0 resistor-2.sym
{
T 51550 47500 5 10 0 0 90 0 1
device=RESISTOR
T 51600 47300 5 10 1 1 90 0 1
refdes=RTest
}
C 46200 47200 1 90 0 voltage-1.sym
{
T 45700 47300 5 10 0 0 90 0 1
device=VOLTAGE_SOURCE
T 45700 47500 5 10 1 1 90 0 1
refdes=V1
}
N 46000 48100 47100 48100 4
N 47100 48100 47100 47800 4
N 46000 47200 47100 47200 4
N 47100 47200 47100 47400 4
N 50500 47800 50500 48400 4
N 50500 48400 51800 48400 4
{
T 50500 48400 5 10 1 0 0 0 1
netname=test
}
N 51800 48400 51800 48000 4
N 50500 47400 50500 46800 4
N 50500 46800 51800 46800 4
{
T 50500 46800 5 10 1 0 0 0 1
netname=test2
}
N 51800 46800 51800 47100 4
***
[EMAIL PROTECTED] test]$ cat testFiltre.cir
***
* Begin .SUBCKT model *
* spice-sdb ver
Re: gEDA-user: poll: How do you geda?
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Here my participation to this poll * What OS do you run geda applications on? Linux Mandriva 2008 * How did you install your copy of geda apps? - From the source package * Which apps do you use. What is your typical workflow? gschem - gspiceui - spice or gnucap - pcb * Did you (have to) modify portions of geda to suit your needs? Not yet * What is the general flavor of your projects? (analog, digital, HF) Mixed, digital and analog for home use. Ludovic SMADJA Kai-Martin Knaak a écrit : I am curious, just how heterogeneous the group of geda users and developers is. So I thought, I'd start this little non-random sample poll in the mailing list: * What OS do you run geda applications on? * How did you install your copy of geda apps? * Which apps do you use. What is your typical workflow? * Did you (have to) modify portions of geda to suit your needs? * What is the general flavor of your projects? (analog, digital, HF) * (add your favorite question here) ---(kaimartin)--- - -- Ludovic SMADJA HALTE AUX SPAMS : Pourquoi signer un email ?? http://www.cacert.org/help.php?id=2lang=fr_FR#whyEmails Clé PGP : 592D0BA1 sur pgp.mit.edu -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mandriva - http://enigmail.mozdev.org iEYEARECAAYFAkhGhOUACgkQS/wVSFktC6F6JwCgk4t1torcLlfy32OWrfhPWShf T0EAn1QUCYXISsxnRxtV74kXcAMyThqc =xBIh -END PGP SIGNATURE- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: howto : strap use in pcb
Hello, I would know how to put straps on my pcb in order to reduce vias. Is it possible and how ? -- Ludovic SMADJA Le hasard, c'est Dieu qui se promène incognito - Albert Einstein HALTE AUX SPAMS : Cet email est signé. Pourquoi signer un email ?? http://www.cacert.org/help.php?id=2lang=fr_FR#whyEmails Mes coordonnées : Jabber ID : [EMAIL PROTECTED] MSN : [EMAIL PROTECTED] Clé PGP : DD76063A sur pgp.mit.edu begin:vcard fn:Ludovic SMADJA n:SMADJA;Ludovic adr:Elancourt;;France email;internet:[EMAIL PROTECTED] note;quoted-printable:JID (jabber ID) : [EMAIL PROTECTED] MSN : [EMAIL PROTECTED] x-mozilla-html:TRUE url:http://Castor-et-herlie.homelinux.org version:2.1 end:vcard signature.asc Description: OpenPGP digital signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: howto : strap use in pcb
Thanks for your answer. It's for me the good solution. regards, Ludovic Mike Jarabek a écrit : Hi, It has been suggested before that you can designate one copper layer for this purpose, and just use vias instead of a footprint. Wherever you want a strap, just draw a copper line. Print the layer seperately and you have a reference for your wires. Doing it this way will allow the DRC to pass and the rats nest will work too. -- Mike Jarabek FPGA/ASIC Designer, DSP Firmware Designer http://www.sentex.ca/~mjarabek -- -Original Message- From: Ludovic SMADJA [EMAIL PROTECTED] Date: Tue, 15 May 2007 21:25:46 To:gEDA user mailing list geda-user@moria.seul.org Subject: gEDA-user: howto : strap use in pcb Hello, I would know how to put straps on my pcb in order to reduce vias. Is it possible and how ? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Ludovic SMADJA Le hasard, c'est Dieu qui se promène incognito - Albert Einstein HALTE AUX SPAMS : Cet email est signé. Pourquoi signer un email ?? http://www.cacert.org/help.php?id=2lang=fr_FR#whyEmails Mes coordonnées : Jabber ID : [EMAIL PROTECTED] MSN : [EMAIL PROTECTED] Clé PGP : DD76063A sur pgp.mit.edu begin:vcard fn:Ludovic SMADJA n:SMADJA;Ludovic adr:Elancourt;;France email;internet:[EMAIL PROTECTED] note;quoted-printable:JID (jabber ID) : [EMAIL PROTECTED] MSN : [EMAIL PROTECTED] x-mozilla-html:TRUE url:http://Castor-et-herlie.homelinux.org version:2.1 end:vcard signature.asc Description: OpenPGP digital signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: avoid route on component layer for specific component
Hi, On an home-made board, it's sometimes quite difficult to solder components on component side. The problem is that autoroute method use it to connect component layer and solder layer. Is a way to easily declare for some components (like IC) but not for others (like resistor) not to route on component layer but only on solder layer ? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: [Proposal] - a new project manager ???
Hi, First, I want to thank you for the great job about gEDA. I use it at home for my leisure and it's a great tool. Except for me, the project manager. I think this program should be improved. I've read that there no manpower about this, so I decided to work about it. Here's a first version of my project manager for gEDA. My C++ is not very strong, so I've written it in java. You could donwload it at http://castor-et-herlie.homelinux.org/gedaGui/gedaGui.tar.bz2 (2.8M). To launch it, you must have java installed on our system (version 1.4.2) , decompress it and in the directory named gedaGui, launch run_gedaGui.sh. The basic of the software is to manage one or multiple project (*.prj but it's not the same file as geda). In a project, you can import files in and the files are sorted by category (text, schematic, pcb layout, ...). For each file there are some commands available(with a right click) like display file info, view content, remove from project and also personal commands. Personal commands are different by category. They are generic and some special string can be used : %f for filename %F for filename without extension %p for project name ex for a schematic, you can launch gschem or run DRC check on it. Commands are defined in a xml file ex. file fileTypeschematic/fileType description/ action labelopen with text editor/label commandkate %f/command /action action labelopen in gschem/label commandgschem %f/command /action action labelcheck DRC errors/label commandgnetlist -g drc2 %f -o %F.drc/command addFileToProject typeFichierdrc report/typeFichier filename%F.drc/filename /addFileToProject /action /file So if you click on open in gschem the program will execute gschem %f, for open with text editor kate %f For drc checking, the program is gnetlist -g drc2 %f -o %F.drc. You may want to add to the application the new generated file (%F.drc) in the project, it's possible to configure for a command some generated file the application have to import automatically after the action (in our example, the file %F.drc will be import as DRC report). My goal was to have a software which is highly configurable so command may be change in the config menu. Here a first version, it works for me and I begin to configure my own command. Feel free to try it, to configure it in order to answer to your needs. Fell also free to contact me if you have any question about it, discover bugs, new features, Of course, source code are available if you want. -- Ludovic SMADJA Le hasard, c'est Dieu qui se promène incognito - Albert Einstein HALTE AUX SPAMS : Cet email est signé. Pourquoi signer un email ?? http://www.cacert.org/help.php?id=2lang=fr_FR#whyEmails Mes coordonnées : Jabber ID : [EMAIL PROTECTED] MSN : [EMAIL PROTECTED] Clé PGP : DD76063A sur pgp.mit.edu begin:vcard fn:Ludovic SMADJA n:SMADJA;Ludovic adr:Elancourt;;France email;internet:[EMAIL PROTECTED] note;quoted-printable:JID (jabber ID) : [EMAIL PROTECTED] MSN : [EMAIL PROTECTED] x-mozilla-html:TRUE url:http://Castor-et-herlie.homelinux.org version:2.1 end:vcard signature.asc Description: OpenPGP digital signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: how to covnert netlist to schema
Ok, thanks for your answer, I'll try to recreate circuit with bom and netlis in a text editor. Ludovic joeft a écrit : ludovic smadja wrote: Hi, I've lost some sch file (which are now garbaged) but netlist are ok. Is there a way to convert a netlist to a schema (a basic schema) ? regards, -- Cordialement, Ludovic SMADJA You may be out of luck. The netlist only contains a small subset of the information that was probably in your schematic. It does not help you to figure out what the schematic symbols looked like or where they were placed on the page etc. The netlist could be a great deal of help in checking or verifying a re-generated schematic however. If you had also generated a BOM however, a lot more of the modified attributes could be captured there. Joe T This message was sent using IMP, the Internet Messaging Program. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- Ludovic SMADJA Le hasard, c'est Dieu qui se promène incognito - Albert Einstein HALTE AUX SPAMS : Cet email est signé. Pourquoi signer un email ?? http://www.cacert.org/help.php?id=2lang=fr_FR#whyEmails Mes coordonnées : Jabber ID : [EMAIL PROTECTED] MSN : [EMAIL PROTECTED] Clé PGP : DD76063A sur pgp.mit.edu begin:vcard fn:Ludovic SMADJA n:SMADJA;Ludovic adr:Elancourt;;France email;internet:[EMAIL PROTECTED] note;quoted-printable:JID (jabber ID) : [EMAIL PROTECTED] MSN : [EMAIL PROTECTED] x-mozilla-html:TRUE url:http://Castor-et-herlie.homelinux.org version:2.1 end:vcard signature.asc Description: OpenPGP digital signature ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
